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PDF PIC16C62B Data sheet ( Hoja de datos )
| Número de pieza | PIC16C62B | |
| Descripción | 28-Pin 8-Bit CMOS Microcontrollers | |
| Fabricantes | Microchip | |
| Logotipo |  |
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PIC16C62B/72A
28-Pin 8-Bit CMOS Microcontrollers
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches, which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of Program Memory,
128 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• In-Circuit Serial Programming(ICSP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 A typical @ 3V, 32 kHz
- < 1 A typical standby current
Pin Diagram
SDIP, SOIC, SSOP, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 RB7
27 RB6
26 RB5
25 RB4
24 RB3
23 RB2
22 RB1
21 RB0/INT
20 VDD
19 VSS
18 RC7
17 RC6
16 RC5/SDO
15 RC4/SDI/SDA
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with Enhanced
SPI and I2C
1998-2013 Microchip Technology Inc.
Preliminary
DS35008C-page 1
1 page  
PIC16C62B/72A
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PIC® MCU
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are two devices (PIC16C62B, PIC16C72A) cov-
ered by this datasheet. The PIC16C62B does not have
the A/D module implemented.
Figure 1-1 is the block diagram for both devices. The
pinouts are listed in Table 1-1.
FIGURE 1-1: PIC16C62B/PIC16C72A BLOCK DIAGRAM
EPROM
2K x 14
Program
Memory
Program
Bus
14
Instruction reg
13
Program Counter
Data Bus
8
8 Level Stack
(13-bit)
RAM
128 x 8
File
Registers
RAM Addr(1)
9
Addr MUX
Direct Addr 7
Indirect
8 Addr
FSR reg
STATUS reg
8
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
Timing
Generation
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
3
MUX
ALU
8
W reg
PORTA
PORTB
PORTC
RA0/AN0(2)
RA1/AN1(2)
RA2/AN2(2)
RA3/AN3/VREF(2)
RA4/T0CKI
RA5/SS/AN4(2)
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
Timer0
MCLR VDD, VSS
Timer1
Timer2
CCP1
Synchronous
Serial Port
A/D(2)
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C62B.
1998-2013 Microchip Technology Inc.
Preliminary
DS35008C-page 5
5 Page 
PIC16C62B/72A
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, the write to these three bits is dis-
abled. These bits are set or cleared according to the
device logic. The TO and PD bits are not writable. The
result of an instruction with the STATUS register as
destination may be different than intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
Note 1: The IRP and RP1 bits are reserved. Main-
tain these bits clear to ensure upward
compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0
R-1
R-1
R/W-x
R/W-x
IRP RP1 RP0 TO
PD
Z
DC
bit7
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
(reserved, maintain clear)
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
Note: RP1 is reserved, maintain clear
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1998-2013 Microchip Technology Inc.
Preliminary
DS35008C-page 11
11 Page | ||
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| PDF Descargar | [ Datasheet PIC16C62B.PDF ] | |
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