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PDF AD5354 Data sheet ( Hoja de datos )
| Número de pieza | AD5354 | |
| Descripción | Low Power 20bit | |
| Fabricantes | AKM | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5354 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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ASAHI KASEI
[AK5354]
AK5354
Low Power 20bit ∆Σ ADC with PGA
FEATURES
The AK5354 is a low voltage 20bit A/D converter for digital audio system. The AK5354 also includes
Analog input PGA, therefore is suitable for microphone application and etc. As digital power supply of the
AK5354 corresponds to 1.8V, the interface with microprocessor can operate at low voltage. Analog signal
input of the AK5354 is single-ended, therefore, any external filters are not required. As the package is
16pin TSSOP, the AK5354 is a suitable for minimizing system.
FEATURES
1. Resolution : 20bits
2. Recording Functions
• 2-Stereo Inputs Selector
• Analog Input PGA
• Monaural Mixing
• Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
3. ADC Characteristics
• Input Level : 1.5Vpp@VA=2.5V (= 0.6 x VA)
• S/(N+D) : 84dB
• DR, S/N : 89dB
4. 3-wire Serial Control I/F
5. Master Clock : 256fs/384fs
6. Audio Data Format : MSB First, 2’s compliment
• 20bit MSB justified or I2S
8. Power Supply
• VA : 2.1 ∼ 3.3V (typ. 2.5V)
• VD : 1.8 ∼ 3.3V (typ. 2.5V)
9. Power Supply Current
• IPGA + ADC : 7mA
10. Ta = -40 ∼ 85°C
11. Package : 16pin TSSOP
LIN1
LIN2
RIN1
RIN2
VCOM
VA
VSS
IPGA
ADC
HPF
Audio I/F
Controller
Control Register I/F
Clock Divider
LRCK
BCLK
SDTO
VD
PDN
CSN CCLK CDTI
MCLK
MS0054-E-02
-1-
2004/12
1 page  
ASAHI KASEI
[AK5354]
FILTER CHARACTERISTICS
(Ta=25°C; VA=2.1 ∼ 3.3V, VD=1.8 ∼ 3.3; fs=44.1kHz)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 5) ±0.1dB
PB
0
-1.0dB
20.0
-3.0dB
21.1
Stopband
(Note 5)
SB
27.0
Passband Ripple
PR
Stopband Attenuation
SA 65
Group Delay
(Note 6)
GD
17.0
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 5) -3dB
FR
3.4
-0.5dB
10
-0.1dB
22
max Units
17.4 kHz
kHz
kHz
kHz
±0.1 dB
dB
1/fs
µs
Hz
Hz
Hz
Note:5. The passband and stopband frequencies scale with fs (sampling frequency).
For examples, PB=0.454 x fs(@ADC: -1.0dB), PB=0.454 x fs(@DAC: -0.1dB).
Note: 6. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to
setting the 20bit data of both channels to the output register for ADC and include group delay of HPF.
(Ta=25°C; VA=2.1 ∼ 3.3V, VD=1.8 ∼ 3.3V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-80µA)
Low-Level Output Voltage (Iout=80µA)
Input Leakage Current
DC CHARACTERISTICS
Symbol
VIH
VIL
VOH
VOL
Iin
min
75%VD
-
VD-0.4
-
-
Typ
-
-
-
-
max
-
25%VD
-
0.4
± 10
Units
V
V
V
V
µA
MS0054-E-02
-5-
2004/12
5 Page 
ASAHI KASEI
[AK5354]
Timing of Control Register
The internal registers are written by the 3-wire µP interface pins: CSN, CCLK, CDTI. These data are included by Op-code
(3bit), Address (LSB-first, 5bit) and Control data (LSB-first, 8bit). A side of transmitted data is output to each bit by “↓”
of CCLK, a side of receiving data is input by “↑” of CCLK. Writing of data becomes effective by “↑” of CSN. CSN
should be held to “H” at no access.
Address except 00H ∼ 03H inhibits control of writing. And CCLK always need 16 edges of “↑” during CSN = “L”.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
op0 op1 op2 A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7
“*” “*” “1”
op0-op2: Op code (Fixed to “**1:WRITE”)
A0-A4: Register Address
D0-D7: Control data
Figure 9. Control Data Timing
Register Map
Addr
00H
01H
02H
03H
Register Name
Input Select
Mode Control 1
Mode Control 2
Input Analog PGA Control
D7
0
0
MONO1
ZEIP
D6
0
0
MONO0
IPGA6
D5
0
0
ZTM1
IPGA5
D4
HPF
0
ZTM0
IPGA4
D3
RIN2
0
0
IPGA3
D2
RIN1
0
0
IPGA2
D1
LIN2
PM1
DIF
IPGA1
D0
LIN1
PM0
0
IPGA0
All registers are reset at PDN = “L”, then inhibits writing to all registers.
MS0054-E-02
- 11 -
2004/12
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AD5354.PDF ] | |
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