PDF MC100E196 Data sheet ( Hoja de datos )

Número de pieza	MC100E196
Descripción	PROGRAMMABLE DELAY CHIP
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Programmable Delay Chip The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control. The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDC’s for increased programmable range. The cascade logic allows full control of multiple PDC’s, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating. MC10E196 MC100E196 PROGRAMMABLE DELAY CHIP • 2.0ns Worst Case Delay Range • ≈20ps/Delay Step Resolution • Linear Input for Tighter Resolution • >1.0GHz Bandwidth • On Chip Cascade Circuitry • Extended 100E VEE Range of –4.2 to –5.46V • 75KΩ Input Pulldown Resistors FN SUFFIX PLASTIC PACKAGE CASE 776-02 PIN NAMES Pin IN/IN EN D[0:7] Q/Q LEN SET MIN SET MAX CASCADE FTUNE Function Signal Input Input Enable Mux Select Inputs Signal Output Latch Enable Min Delay Set Max Delay Set Cascade Signal Linear Voltage Input VBB IN IN 11 EN * 1.25 0 1 * 1.5 0 1 LEN SET MIN SET MAX 0 11 LOGIC DIAGRAM – SIMPLIFIED 0 1 11 4 GATES 0 1 7 BIT LATCH 8 GATES 0 1 16 GATES LEN Q LATCH D FTUNE 0 1 0 11 CASCADE LINEAR RAMP Q Q CASCADE CASCADE D0 D1 D2 D3 D4 D5 D6 * DELAYS ARE 25% OR 50% LONGER THAN * STANDARD (STANDARD ≈ 80 PS) D7 12/93 © Motorola, Inc. 1996 2–1 REV 2 1 page TO SELECT MULTIPLEXERS MC10E196 MC100E196 BIT 0 D0 Q0 LEN Reset Reset SET MIN SET MAX BIT 1 D1 Q1 LEN Reset Reset BIT 2 D2 Q2 LEN Reset Reset BIT 3 D3 Q3 LEN Reset Reset BIT 4 D4 Q4 LEN Reset Reset BIT 5 D5 Q5 LEN Reset Reset BIT 6 D6 Q6 LEN Reset Reset BIT 7 D7 Q7 LEN Reset Reset Figure 2. Expansion of the Latch Section of the E195 Block Diagram CASCADE CASCADE ECLinPS and ECLinPS Lite DL140 — Rev 4 2–5 MOTOROLA 5 Page

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