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PDF MC100EL14 Data sheet ( Hoja de datos )
| Número de pieza | MC100EL14 | |
| Descripción | 1:5 Clock Distribution Chip | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC100EL14 (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:5 Clock Distribution Chip
The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. The LVEL14 is
functionally and pin compatible with the EL14 but is designed to operate
in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or
3.0V to 3.8V). If a single-ended input is to be used the VBB output should
be connected to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the switching reference
for the input of the LVEL14 under single-ended input conditions, as a
result this pin can only source/sink up to 0.5mA of current.
The LVEL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by the input
pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This avoids
any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock, therefore
all associated specification limits are referenced to the negative edge of
the clock input.
• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Multiplexed Clock Input
• 75kΩ Internal Input Pulldown Resistors
• >2000V ESD Protection
• VEE Range of –3.0V to –5.5V
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC EN VCC NC SCLK CLK CLK VBB SEL VEE
20 19 18 17 16 15 14 13 12 11
10
D
Q
1 2 3 4 5 6 7 8 9 10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4
MC100LVEL14
MC100EL14
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN DESCRIPTION
PIN FUNCTION
CLK
SCLK
EN
SEL
VBB
Q0–4
Diff Clock Inputs
Scan Clock Input
Sync Enable
Clock Select Input
Reference Output
Diff Clock Outputs
FUNCTION TABLE
CLK SCLK SEL EN
L X LL
H X LL
X L HL
X H HL
X X XH
* On next negative transition of
CLK or SCLK
Q
L
H
L
H
L*
7/95
© Motorola, Inc. 1996
4–1
REV 1
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet MC100EL14.PDF ] | |
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