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PDF MC100LVEL38 Data sheet ( Hoja de datos )
| Número de pieza | MC100LVEL38 | |
| Descripción | Clock Generation Chip | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
÷2, ÷4/6 Clock Generation Chip
The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
MC100EL38 is pin and functionally equivalent to the MC100LVEL38 but
is specified for operation at the standard 100K ECL voltage supply. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended LVECL or, if positive power supplies are
used, LVPECL input signal. In addition, by using the VBB output, a
sinusoidal source can be AC coupled into the device (see Interfacing
section of the ECLinPS™ Data Book DL140/D). If a single-ended input is
to be used, the VBB output should be connected to the CLK input and
bypassed to ground via a 0.01µF capacitor. The VBB output is designed to
act as the switching reference for the input of the LVEL38 under
single-ended input conditions, as a result, this pin can only source/sink up
to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever the
÷2 and the ÷4/6 outputs are both transitioning from a LOW to a HIGH.
This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2 and the ÷4/6 outputs of a
single device.
• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kΩ Internal Input Pulldown Resistors
• >1500V ESD Protection
• Low Voltage VEE Range of –3.0 to –3.8V
Pinout: 20-Lead SOIC (Top View)
VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE
20 19 18 17 16 15 14 13 12 11
12345678
VCC EN DIV_SEL CLK CLK VBB MR VCC
9
10
MC100LVEL38
MC100EL38
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN DESCRIPTION
PIN FUNCTION
CLK
EN
MR
VBB
Q0, Q1
Q2, Q3
DIVSEL
Phase_Out
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff ÷2 Outputs
Diff ÷4/6 Outputs
Frequency Select Input
Phase Sync Signal
CLK
FUNCTION TABLE
EN MR FUNCTION
ZL
ZZ H
XX
L
L
H
Z = Low-to-High Transition
ZZ = High-to-Low Transition
Divide
Hold Q0–3
Reset Q0–3
DIVSEL
0
1
Q2, Q3 OUTPUTS
Divide by 4
Divide by 6
10/94
© Motorola, Inc. 1996
4–1
REV 1
1 page  
OUTLINE DIMENSIONS
–A
–
20
11
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–B P 10 PL
– 0.010 (0.25) M B M
1 10
D 20 PL
0.010 (0.25) M T A S B S
J
F
R X 45°
G 18 PL
C
–T
SE–ATING
K PLANE
M
MC100LVEL38 MC100EL38
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC
0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
MFAX: [email protected] – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
ECLinPS and ECLinPS Lite
DL140 — Rev 3
◊
*MC100LVEL38/D*MC100LVEL38/D
4–5 MOTOROLA
5 Page | ||
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| PDF Descargar | [ Datasheet MC100LVEL38.PDF ] | |
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