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PDF CY7C136A Data sheet ( Hoja de datos )
| Número de pieza | CY7C136A | |
| Descripción | 2K x 8 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C132, CY7C136
CY7C136A, CY7C142,
CY7C146
2K x 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells that enable simultaneous reads
of the same memory location
■ 2K x 8 organization
■ 0.65 micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: ICC = 110 mA (maximum)
■ Fully asynchronous operation
■ Automatic power-down
■ Master CY7C132/CY7C136/CY7C136A[1] easily expands data
bus width to 16 or more bits using slave CY7C142/CY7C146
■ BUSY output flag on CY7C132/CY7C136/CY7C136A;
BUSY input on CY7C142/CY7C146
■ INT flag for port to port communication (52-Pin PLCC/PQFP
versions)
■ CY7C136, CY7C136A, and CY7C146 available in 52-pin
PLCC and 52-pin PQFP packages
■ Pb-free packages available
Functional Description
The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146
are high speed CMOS 2K x 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132, CY7C136, and CY7C136A can be used
as either a standalone 8-bit dual-port static RAM or as a
MASTER dual-port RAM, in conjunction with the
CY7C142/CY7C146 SLAVE dual-port device. They are used in
systems that require 16-bit or greater word widths. This is the
solution to applications that require shared or buffered data, such
as cache memory for DSP, bit-slice, or multiprocessor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). BUSY flags are provided
on each port. In addition, an interrupt flag (INT) is provided on
each port of the 52-pin PLCC version. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. On the PLCC version, INT is an interrupt flag
indicating that data is placed in an unique location (7FF for the
left port and 7FE for the right port).
An automatic power-down feature is controlled independently on
each port by the chip enable (CE) pins.
Logic Block Diagram
R/WL
CEL
OEL
R/WR
CER
OER
I/O7L
I/O0L
BUSYL[2]
A 10L
A 0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
I/O7R
I/O0R
[2]
BUSYR
A 10R
A 0R
INTL[3]
CEL
OEL
R/WL
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
CER
OER
R/WR
[3]
INTR
Notes
1. CY7C136 and CY7C136A are functionally identical.
2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.
3. Open drain outputs; pull up resistor required.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06031 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 14, 2011
1 page  
CY7C132, CY7C136
CY7C136A, CY7C142,
CY7C146
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30) [8] (continued)
Parameter
Description
Write Cycle[12]
tWC Write Cycle Time
tSCE
CE LOW to Write End
tAW Address Setup to Write End
tHA Address Hold from Write End
tSA Address Setup to Write Start
tPWE
R/W Pulse Width
tSD Data Setup to Write End
tHD
tHZWE
tLZWE
Data Hold from Write End
R/W LOW to High Z [7]
R/W HIGH to Low Z [7]
Busy/Interrupt Timing
tBLA
tBHA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[13]
tBLC
tBHC
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[13]
tPS Port Set Up for Priority
tWB R/W LOW after BUSY LOW[14]
tWH R/W HIGH after BUSY HIGH
tBDD
BUSY HIGH to Valid Data
tDDD
Write Data Valid to Read Data Valid
tWDD
Write Pulse to Data Delay
Interrupt Timing [16]
tWINS
R/W to INTERRUPT Set Time
tEINS
CE to INTERRUPT Set Time
tINS
tOINR
tEINR
tINR
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[13]
CE to INTERRUPT Reset Time[13]
Address to INTERRUPT Reset Time[13]
Shaded areas contain preliminary information.
7C136-15 [4]
7C146-15
Min Max
15
12
12
2
0
12
10
0
10
0
15
15
15
15
5
0
13
15
Note 15
Note 15
15
15
15
15
15
15
7C132-25 [4]
7C136-25
7C142-25
7C146-25
Min Max
25
20
20
2
0
15
15
0
15
0
20
20
20
20
5
0
20
25
Note 15
Note 15
25
25
25
25
25
25
7C132-30
7C136-30
7C142-30
7C146-30
Min Max
30
25
25
2
0
25
15
0
15
0
20
20
20
20
5
0
30
30
Note 15
Note 15
25
25
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
14. CY7C142/CY7C146 only.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
16. 52-pin PLCC and PQFP versions only.
Document #: 38-06031 Rev. *H
Page 5 of 17
5 Page 
CY7C132, CY7C136
CY7C136A, CY7C142,
CY7C146
Switching Waveforms (continued)
Interrupt Timing Diagrams [16]
ADDRESSL
CEL
Figure 12. Left Side Sets INTR
tWC
WRITE 7FF
tINS tHA
R/WL
INTR
tEINS
tSA
tWINS
ADDRESSR
CER
R/WR
Figure 13. Right Side Clears INTR
tRC
READ 7FF
tHA tINR
tEINR
OER
INTR
ADDRESSR
CER
R/WR
INTL
tOINR
Figure 14. Right Side Sets INTL
tWC
WRITE 7FE
tINS tHA
tEINS
tSA tWINS
ADDRESSL
CEL
R/WL
OEL
INTL
Figure 15. Right Side Clears INTL
tRC
READ 7FE
tHA tINR
tEINR
tOINR
Document #: 38-06031 Rev. *H
Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY7C136A.PDF ] | |
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