PDF AS4C8M16SA Data sheet ( Hoja de datos )

Número de pieza	AS4C8M16SA
Descripción	128M - 8M x 16 bit Synchronous DRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! AS4C8M16SA Confidential 128M - 8M x 16 bit Synchronous DRAM (SDRAM) (Rev. 2.2, March 2014) Features  Fast access time from clock: 5/5.4 ns  Fast clock rate: 166/143 MHz  Fully synchronous operation  Internal pipelined architecture  2M word x 16-bit x 4-bank  Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function  Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C)  Auto Refresh and Self Refresh  4096 refresh cycles/64ms  CKE power down mode  Single +3.3V  0.3V power supply  Interface: LVTTL  54-pin 400 mil plastic TSOP II package  54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package All parts ROHS Compliant Overview The 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications. Table 1. Key Specifications AS4C16M16S tCK3 Clock Cycle time (min.) tAC3 Access time from CLK (max.) tRAS Row Active time (min.) tRC Row Cycle time (min.) -6/7 6/7 ns 5.4/5.4 ns 42/42 ns 60/63 ns Table 2. Ordering Information Part Number Frequency Package AS4C8M16SA-7TCN 143 MHz 54 pin TSOP II AS4C8M16SA-6TCN AS4C8M16SA-6TIN 166 MHz 166 MHz 54 pin TSOP II 54 pin TSOP II AS4C8M16SA-6BIN AS4C8M16SA-7BCN T : indicates TSOP II package B : indicates TFBGA package 166 MHz 143 MHz 54 ball TFBGA 54 ball TFBGA N : indicates Pb free and Halogen free – ROHS compliant parts C: Commercial I: Industrial Confidential 1 Rev. 2.2 Mar /2014 1 page AS4C8M16SA WE# LDQM, UDQM DQ0-DQ15 NC/RFU VDDQ VSSQ VDD VSS Input Input Input / Output - Supply Supply Supply Supply Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode. Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskable during Reads and Writes. No Connect: These pins should be left unconnected. DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V 0.3V ) DQ Ground: Provide isolated ground to DQs for improved noise immunity. (0V) Power Supply: +3.3V  0.3V Ground Confidential 5 Rev. 2.2 Mar /2014 5 Page AS4C8M16SA CLK COMMAND T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP WRITE A READ B NOP NOP NOP NOP NOP NOP CAS# Latency=2 tCK2, DQ DIN A0 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS# Latency=3 tCK3, DQ DIN A0 don’t care don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 T7 CLK DQM COMMAND WRITE NOP NOP Precharge tRP NOP NOP Activate NOP ADDRESS DQ Bank Col n DIN n tWR DIN N+1 Bank (s) ROW Don’t Care Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2. Figure 13. Write to Precharge 7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A8 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP (min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. Confidential 11 Rev. 2.2 Mar /2014 11 Page

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