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PDF CY7C1386S Data sheet ( Hoja de datos )
| Número de pieza | CY7C1386S | |
| Descripción | 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM | |
| Fabricantes | Cypress | |
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CY7C1386S
18-Mbit (512 K × 36) Pipelined DCD Sync
SRAM
18-Mbit (512 K × 36) Pipelined DCD Sync SRAM
Features
■ Supports bus operation up to 167 MHz
■ Available speed grade is 167 MHz
■ Registered inputs and outputs for pipelined operation
■ Optimal for performance (double-cycle deselect)
■ Depth expansion without wait state
■ 3.3 V core power supply (VDD)
■ 2.5 V or 3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 3.4 ns (for 167 MHz device)
■ Provides high-performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed writes
■ Asynchronous output enable
■ Available in JEDEC-standard Pb-free 100-pin TQFP
■ ZZ sleep mode option
Functional Description
The CY7C1386S SRAM integrates 512 K × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Configurations on page 4 and Truth Table on
page 8 for further details). Write cycles can be one to four bytes
wide as controlled by the byte write control inputs. GW active
LOW writes all bytes. This device incorporates an additional
pipelined enable register which delays turning off the output
buffers an additional cycle when a deselect is executed.This
feature allows depth expansion without penalizing system
performance.
The CY7C1386S operates from a +3.3 V core power supply
while all outputs operate with a +3.3 V or +2.5 V supply. All inputs
and outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
167 MHz
3.4
275
70
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-43823 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 22, 2013
1 page  
CY7C1386S
Pin Definitions
Name
I/O
Description
A0, A1, A
Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit
counter.
BWA, BWB,
Input- Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWC, BWD Synchronous Sampled on the rising edge of CLK.
GW Input- Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
Input- Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
CLK Input- Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
Clock counter when ADV is asserted LOW, during a burst operation.
CE1 Input- Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2 Input- Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3 Input- Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE Input- Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input- Advance Input Signal, Sampled on the Rising Edge of Clk, Active LOW. When asserted, it automat-
Synchronous ically increments the address in a burst cycle.
ADSP
ADSC
Input- Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
Input- Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ Input- ZZ Sleep Input, Active High. When asserted HIGH places the device in a non-time critical sleep
Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW. ZZ pin has an internal
pull down.
DQs, DQPX I/O- Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.
VDD
VSS
VSSQ
VDDQ
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Core of the Device.
I/O Ground Ground for the I/O Circuitry.
I/O Power Power Supply for the I/O Circuitry.
Supply
Document Number: 001-43823 Rev. *E
Page 5 of 22
5 Page 
CY7C1386S
Capacitance
Parameter [11]
Description
CIN
CCLK
CIO
Input capacitance
Clock input capacitance
Input/Output capacitance
Thermal Resistance
Parameter [11]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP
Max
5
5
5
Unit
pF
pF
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
28.66
4.08
°C/W
°C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z0 = 50
3.3V
OUTPUT
RL = 50
5 pF
VT = 1.5V
(a)
2.5V I/O Test Load
INCLUDING
JIG AND
SCOPE
OUTPUT
Z0 = 50
2.5V
OUTPUT
RL = 50
5 pF
VT = 1.25V
(a)
INCLUDING
JIG AND
SCOPE
R = 317
R = 351
VDDQ
GND
ALL INPUT PULSES
10%
90%
1 ns
90%
10%
1 ns
(b) (c)
R = 1667
R = 1538
VDDQ
GND
10%
1 ns
ALL INPUT PULSES
90%
90%
10%
1 ns
(b) (c)
Note
11. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-43823 Rev. *E
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY7C1386S.PDF ] | |
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