|
|
PDF CY7C1371S Data sheet ( Hoja de datos )
| Número de pieza | CY7C1371S | |
| Descripción | 18-Mbit (512K x 36) Flow-Through SRAM | |
| Fabricantes | Cypress | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1371S (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
|
No Preview Available !
CY7C1371S
18-Mbit (512K × 36) Flow-Through SRAM
with NoBL™ Architecture
18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture
Features
■ No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states
■ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte Write capability
■ 3.3 V/2.5 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock Enable (CEN) pin to enable clock and suspend operation
■ Synchronous self-timed writes
■ Asynchronous Output Enable
■ Available in JEDEC-standard Pb-free 100-pin TQFP, and non
Pb-free 119-ball BGA
■ Three chip enables for simple depth expansion
■ Automatic Power down feature available using ZZ mode or CE
deselect
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ Burst Capability – linear or interleaved burst order
■ Low standby power
Functional Description
The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations with no wait state insertion.
The CY7C1371S is equipped with the advanced No Bus Latency
(NoBL) logic required to enable consecutive Read/Write opera-
tions with data being transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent Write-Read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz
6.5
210
70
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-43826 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 18, 2016
1 page  
CY7C1371S
Pin Configurations (continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout
CY7C1371S (512K × 36)
1 234
A VDDQ
A
A
A
B NC/576M CE2
C NC/1G
A
A ADV/LD
A VDD
D
DQC
DQPC
VSS
E DQC DQC VSS
F
VDDQ
DQC
VSS
NC
CE1
OE
G DQC DQC BWC
A
H DQC DQC VSS
WE
J VDDQ VDD NC VDD
K DQD DQD VSS CLK
L
DQD
DQD
BWD
NC
M VDDQ DQD VSS CEN
N DQD DQD VSS
A1
P
DQD
DQPD
VSS
A0
R NC/144M A
MODE
VDD
T NC NC/72M A
A
U VDDQ TMS TDI TCK
5
A
A
A
VSS
VSS
VSS
BWB
VSS
NC
VSS
BWA
VSS
VSS
VSS
NC
A
TDO
67
A VDDQ
CE3 NC
A NC
DQPB
DQB
DQB
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQPA
A
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
DQA
NC/288M
NC/36M
NC
ZZ
VDDQ
Document Number: 001-43826 Rev. *F
Page 5 of 29
5 Page 
CY7C1371S
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the shift-DR controller state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is supplied a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High Z
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells prior to the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-ball BGA package). When this scan cell, called the
“extest output bus tri-state,” is latched into the preload register
during the “Update-DR” state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-43826 Rev. *F
Page 11 of 29
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet CY7C1371S.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1371B | (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM |  Cypress Semiconductor |
| CY7C1371C | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture | Cypress |
| CY7C1371D | 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM | Cypress Semiconductor |
| CY7C1371DV25 | (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |