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PDF CY7C1061G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1061G | |
| Descripción | 16-Mbit (1 M words x 16 bit) Static RAM | |
| Fabricantes | Cypress | |
| Logotipo |  |
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CY7C1061G Automotive
16-Mbit (1 M words × 16 bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ High speed
❐ tAA = 10 ns
■ Temperature range
❐ Automotive-E: –40 °C to 125 °C
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Low active and standby currents
❐ ICC = 90-mA typical at 100 MHz
❐ ISB2 = 20-mA typical
■ Operating voltage range: 2.2 V to 3.6 V
■ 1.0-V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY7C1061G[1] is a high-performance CMOS fast static RAM
automotive part with embedded ECC. ECC logic can detect and
correct single-bit error in read data word during read cycles.
This device has single chip enable input and is accessed by
asserting the chip enable input (CE) LOW.
To perform data writes, assert the Write Enable (WE) input LOW
and provide the data and address on the device data pins (I/O0
through I/O15) and address pins (A0 through A19) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE), inputs
control byte writes and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. Read data is
accessible on I/O lines (I/O0 through I/O15). You can perform
byte accesses by asserting the required byte enable signal (BHE
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH), or control signals are
de-asserted (OE, BLE, BHE). Refer to the below logic block
diagram.
The CY7C1061G automotive device is available in 48-ball
VFBGA and 48-pin TSOP I packages.
Logic Block Diagram – CY7C1061G
ECC EN CO DER
INPU T BU FFER
A0
A1
A2
A3
A4
M EM ORY
A5 ARRAY
A6
A7
A8
A9
CO LU M N DECO DER
I/O 0‐I/O 7
I/O 8‐I/O 15
Note
1. The device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84821 Rev. *H
BHE
WE
OE
BLE
CE
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 28, 2015
1 page  
CY7C1061G Automotive
Capacitance
Parameter [6]
Description
CIN
COUT
Input capacitance
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
All Packages
10
10
Unit
pF
pF
Thermal Resistance
Parameter [6]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
48-ball VFBGA 48-pin TSOP I Unit
31.50
57.99
C/W
15.75
13.42
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [7]
Output
Z0 = 50
(a)
* Capacitive load consists
of all components of the
test environment
50
30 pF*
VTH
VHIGH
90%
GND
10%
Rise Time:
> 1 V/ns
All Input Pulses
(c)
High-Z Characteristics:
VCC
Output
R1
5 pF*
* Including
JIG and
Scope
(b)
90%
10%
Fall Time:
> 1 V/ns
R2
Parameters
R1
R2
VTH
VHIGH
3.0 V
317
351
1.5
3
Unit
V
V
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and 100-µs wait time after VCC stabilizes to its operational value.
Document Number: 001-84821 Rev. *H
Page 5 of 18
5 Page 
CY7C1061G Automotive
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (BLE or BHE Controlled) [27, 28]
tWC
ADDRESS
CE
BHE/
BLE
tSA
WE
DATA I/O
Note 29
tHZWE
tSCE
tAW
tBW
tHA
tPWE
tSD tHD
DATAIN VALID
tLZWE
Notes
27.
The internal write
HIGH transition of
taimnyeoofftthheesemseimgnoarylsicsadnetfeinremdinbaytethteheooveprelaraptioofnW. TEhe=inVpILu,tCdEata=
sVeILtu, panadndBhHoEldotrimBiLnEg
s=hVoIuLl.dTbheesreefesrigennacelsdmtoutshtebeedLgOeWof
to initiate a write, and the
the signal that terminates
the write.
28. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
29. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-84821 Rev. *H
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY7C1061G.PDF ] | |
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