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PDF PI6C557-06 Data sheet ( Hoja de datos )
| Número de pieza | PI6C557-06 | |
| Descripción | 1:4 HCSL PCIe Buffer | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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Features
ÎÎ1:4 HCSL clock buffer
ÎÎPCIe® Gen 1, 2 and 3 compliant
ÎÎSelectable reference inputs
ÎÎCycle-to-Cycle Jitter <70ps
ÎÎOutput-to-Output Skew <35ps
ÎÎ3.3V supply voltage
ÎÎTSSOP-20 package
ÎÎIndustrial Temperature
Applications
ÎÎServers
ÎÎEmbedded computing systems
ÎÎNetworking systems
Block Diagram
OE
SRCIN1
SRCIN1#
SRCIN2
SRCIN2#
REFSEL
PD#
PI6C557-06
1:4 HCSL PCIe® Buffer
Description
The PI6C557-06 is a high performance PCIe® buffer with four
HCSL outputs compliant to PCIe® Gen 1, 2 and 3 standards. The
device has selectable reference inputs to provide flexibility in sys-
tem design.
Pin Configuration
CLK0
CLK0#
CLK1
CLK1#
CLK2
CLK2#
CLK3
CLK3#
REFSEL
VDDIN
SRCIN1
SRCIN1#
PD#
SRCIN2
SRCIN2#
OE
GND
IRef
1
2
3
4
5
6
7
8
9
10
20 CLK0
19 CLK0#
18 CLK1
17 CLK1#
16 GND
15 VDDOUT
14 CLK2
13 CLK2#
12 CLK3
11 CLK3#
All trademarks are property of their respective owners.
11-0051
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P-0.1
09/15/10
1 page  
PI6C557-06
1:4 HCSL PCIe Buffer
HCSL AC Electrical Characteristics (Over Operating Conditions)
Symbol
Fin
FOUT
Tr /Tf
ΔTr /ΔTf
TPD
Tskew
TDC
JC
JAdd
JPhase
PSR
TOEN
TOEF
Parameter
Input Frequency
Output Frequency
Output Rise/Fall time
Rise and Fall Time Variation(2)
Propagation delay
Output-to-Output Skew(3)
Output Duty Cycle(3)
Cycle to cycle jitter (3)
Additive RMS jitter (4)
Additive RMS jitter for PCIe 2.0
RMS phase jitter for PCIe 3.0
Power Supply Noise Rejection
OE enable time
OE disable time
Conditions
-
HCSL termination
Between 0.175V and 0.525V(2)
-
Input to output measured at the
mid point level
-
-
Differential waveform
100MHz HCSL from 12 kHz to
20MHz
High Frequency
Low Frequency
50mVp-p input sine wave 100kHz
to 600kHz(2)
Min.
-
-
175
-
-
-
47
-
-
<0
-
-
-
Notes:
1. For LVDS Termination , the maximum frequency is 100MHz
2. Measurement is taken from Single Ended waveform.
3. Measurement is taken from Differential waveform.
4. Additive jitter is calculated from input and output RMS phase jitter. (Ja = √(output jitter)2 – (input jitter)2
Typ.
-
-
-
-
3.0
-
-
50
330
-
0.4
0.6
-53
Max.
200
200(1)
700
125
4.5
35
53
70
-
1
1
3
-
100
100
Unit
MHz
MHz
ps
ps
ns
ps
%
ps
fs
ps
ps
ps
dBc
ns
ns
All trademarks are property of their respective owners.
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5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PI6C557-06.PDF ] | |
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