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PDF SS2015 Data sheet ( Hoja de datos )
| Número de pieza | SS2015 | |
| Descripción | CMOS High Sensitivity Micropower Hall Latch | |
| Fabricantes | SEC | |
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Hay una vista previa y un enlace de descarga de SS2015 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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Packages
SS2015
CMOS High Sensitivity Micropower Hall Latch
3 pin SIP (suffix UA)
Features and Benefits
1. Operation down to 4.5V
2. Wide operating voltage range
3. High sensitivity for direct reed switch re-
placement applications
4. Output switches with absolute
value of North or South pole from magnet
5. Temperature compensation
6. Open-Collector pre-driver
7. 60V maximum withstand voltage
8. Reverse polarity protection
9. Package: TO-92S(SIP)
Functional Block Diagram
Application Examples
1. Brush-less DC Motor
2. Brush-less DC Fan
3. Revolution counting
4. Speed measurement
General Description:
The SS2015 Hall effect latch sensor IC is fabricated from mixed signal CMOS technology. It incorporates ad-
vanced chopper-stabilization techniques to provide accurate and stable magnetic switch points.
The circuit design provides an internally controlled clocking mechanism to cycle power to the Hall element and
analog signal processing circuits. This serves to place the high current-consuming portions of the circuit into a
“Sleep” mode. Periodically the device is “Awakened” by this internal logic and the magnetic flux from the Hall
element is evaluated against the predefined thresholds. If the flux density is above or below the BOP/BRP thresh-
olds then the output transistor is driven to change states accordingly. While in the “Sleep” cycle the output tran-
sistor is latched in its previous state. The design has been optimized for service in applications requiring extended
operating lifetime in battery powered systems. An internal bandgap regulator is used to provide temperature com-
pensated supply voltage for internal circuits and allows a wide operating supply range.
The output transistor of the SS2015 will be latched on (BOP) in the presence of a sufficiently strong South or
North magnetic field facing the marked side of the package. The output will be latched off (BRP) in the absence
of a magnetic field.
1 V3.10 Nov 1, 2013
1 page  
SS2015
CMOS High Sensitivity Micropower Hall Latch
ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
5 V3.10 Nov 1, 2013
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet SS2015.PDF ] | |
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