|
|
PDF CS4224 Data sheet ( Hoja de datos )
| Número de pieza | CS4224 | |
| Descripción | 24-Bit 105 dB Audio Codec with Volume Control | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CS4224 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CS4223
CS4224
24-Bit 105 dB Audio Codec with Volume Control
Features
105 dB Dynamic Range A/D Converters
105 dB Dynamic Range D/A Converters
110 dB DAC Signal-to-Noise Ratio (EIAJ)
Analog Volume Control (CS4224 only)
Differential Inputs / Outputs
On-chip Anti-aliasing and Output Smoothing
Filters
De-emphasis for 32, 44.1 and 48 kHz
Supports Master and Slave Modes
Single +5 V power supply
On-Chip Crystal Oscillator
3 - 5 V Digital Interface
Description
The CS4223/4 is a highly integrated, high performance,
24-bit, audio codec providing stereo analog-to-digital and
stereo digital-to-analog converters using delta-sigma
conversion techniques. The device operates from a sin-
gle +5 V power supply, and features low power
consumption. Selectable de-emphasis filter for 32, 44.1,
and 48 kHz sample rates is also included.
The CS4224 includes an analog volume control capable
of 113.5 dB attenuation in 0.5 dB steps. The analog vol-
ume control architecture preserves dynamic range
during attenuation. Volume control changes are imple-
mented using a “soft” ramping or zero crossing
technique.
Applications include digital effects processors, DAT, and
multitrack recorders.
ORDERING INFORMATION
CS4223-KS -10 to +70 °C 28-pin SSOP
CS4223-BS -40 to +85 °C 28-pin SSOP
CS4223-DS -40 to +85 °C 28-pin SSOP
CS4224-KS -10 to +70 °C 28-pin SSOP
CDB4223/4
Evaluation Board
I
(DIF1)
(DIF0) (DEM0) (DEM1)
SCL/CCLK SDA/CDIN AD0/CS I2C/SPI
VL MCLK VD VA
RST
LRCK
SCLK
SDIN
SDOUT
Control Port
Left
DAC
Right
DAC
Clock OSC
Left
ADC
Right
ADC
Volume *
Control
Voltage
Reference
Volume *
Control
AOUTL+
AOUTL-
AOUTR+
AOUTR-
AINL-
AINL+
AINR-
AINR+
XTI XTO
( ) = CS4223
DGND
* = CS4224
AGND
Cirrus Logic, Inc.
http://www.cirrus.com
©Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
JAN ‘03
DS290F1
1
1 page  
CS4223 CS4224
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(AGND, DGND = 0 V, all voltages with respect to 0 V.)
Power Supplies
Parameter
Ambient Operating Temperature
Digital
Analog
Digital
| VA - VD |
Commercial (-KS)
Industrial (-BS/-DS)
Symbol
VD
VA
VL
TAC
TAI
Min
4.75
4.75
2.7
-
-10
-40
Nom
5.0
5.0
5.0
-
-
-
Max Unit
5.25
5.25
5.25
0.4
V
V
V
V
70 °C
85 °C
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)
Power Supplies
Parameter
Input Current
Analog Input Voltage
Digital Input Voltage
Ambient Temperature
Storage Temperature
Digital
Analog
(Note 1)
(Note 2)
(Note 2)
Power Applied
Symbol
VD
VA
Min
-0.3
-0.3
-
-0.7
-0.7
-55
-65
Max
6.0
6.0
±10
VA + 0.7
VD + 0.7
+125
+150
Unit
V
V
mA
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR
latch-up.
2. The maximum over or under voltage is limited by the input current.
DS290F1
5
5 Page 
CS4223 CS4224
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MODE (CS4224)
(Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF)
Parameter
Symbol
Min
Max Unit
I2C® Mode (SPI/I2C = 1)
SCL Clock Frequency
RST rising edge to Start
(Note 15)
Bus Free Time between transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup time for repeated Start Condition
SDA hold time for SCL falling
(Note 16)
SDA setup time to SCL rising
Rise time of SCL
Fall time of SCL
Rise time of SDA
Fall time of SDA
Setup time for Stop Condition
fscl
tirs
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
trc
tfc
trd
tfd
tsusp
-
50
4.7
4.0
4.7
4.0
4.7
0
250
-
-
-
-
4.7
100 kHz
- µs
- µs
- µs
- µs
- µs
- µs
- µs
- ns
25 ns
25 ns
1 µs
300 ns
- µs
Notes: 15. Not tested but guaranteed by design.
16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t irs
Stop
Start
SDA
SCL
t buf t hdst
t high
t low t hdd
Repeated
Start t rd
t hdst
t fc
t sud
t sust
t rc
Stop
t fd
t susp
Figure 3. I2C Control Port Timing
DS290F1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4224.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CS4220 | 24-Bit Stereo Audio Codec with 3V Interface | Cirrus Logic |
| CS4220-KS | 24-Bit Stereo Audio Codec with 3V Interface | Cirrus Logic |
| CS4221 | 24-Bit Stereo Audio Codec with 3V Interface | Cirrus Logic |
| CS4221-KS | 24-Bit Stereo Audio Codec with 3V Interface | Cirrus Logic |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |