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PDF LTC3896 Data sheet ( Hoja de datos )
| Número de pieza | LTC3896 | |
| Descripción | Inverting DC/DC Controller | |
| Fabricantes | Linear | |
| Logotipo |  |
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LTC3896
150V Low IQ, Synchronous
Inverting DC/DC Controller
Features
Description
nn Wide VIN + |VOUT–| Range: 4V to 140V (150V Abs Max)
nn Wide Output Voltage Range: –60V to –0.8V
nn Ground-Referenced Control / Interface Pins
nn Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE)
nn Integrated Bootstrap Diode
nn Low Operating IQ: 40μA (Shutdown = 10μA)
nn Selectable Gate Drive UVLO Thresholds
nn Onboard LDO or External NMOS LDO for DRVCC
nn EXTVCC LDO Powers Drivers from Output
nn Phase-Lockable Frequency (75kHz to 850kHz)
nn Programmable Fixed Frequency (50kHz to 900kHz)
nn Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode® Operation at Light Loads
nn Adjustable Burst Clamp and Current Limit
nn Power Good Output Voltage Monitor
nn Programmable Input Overvoltage Lockout
nn 38-Lead TSSOP High Voltage Package
Applications
nn Automotive and Industrial Power Systems
nn Telecommunications Power Supplies
nn Distributed Power Systems
The LTC®3896 is a high performance inverting DC/DC
switching regulator controller that drives an all N-channel
synchronous power MOSFET stage. It converts a wide-
ranging positive input voltage source to a regulated negative
output that can be as much as 60V below ground. The
input can operate from a voltage as low as 4V and as high
as 140V – |VOUT–|.
The LTC3896 contains true ground-referenced RUN, PLLIN
and PGOOD pins, eliminating the need for external discrete
level-shifting components to interface with the LTC3896.
A constant frequency current mode architecture allows a
phase-lockable frequency of up to 850kHz. The low 40μA
no-load quiescent current extends operating run time in
battery-powered systems. OPTI-LOOP® compensation
allows the transient response to be optimized over a
wide range of output capacitance and ESR values. The
LTC3896 features a precision 0.8V reference and power
good output indicator. The soft-start (SS) pin ramps the
output voltage during start-up.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and OPTI-LOOP are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620,
6144194, 6177787, 6580258.
Typical Application
High Efficiency 36V–72V to –48V/2A Inverting Regulator
VIN
36V to 72V
0.1µF
×3
47µF 0V
0V
5V
100k
4.7µF
0.1µF
301k
0.1µF
100pF
4.99k
15nF
RUN VIN
TG
PLLIN
GND BOOST
PGOOD
NDRV LTC3896
SW
DRVCC
INTVCC
DRVSET
SENSE+
DRVUV
SENSE–
SS
ITH BG
FREQ VOUT–
VFB
0.1µF
47µH
10mΩ
590k
10k
3896 TA01a
VOUT–
–48V
2A
4.7µF
100V
2220
×4
For more information www.linear.com/LTC3896
Efficiency and Power Loss
vs Load Current
100 100k
90 EFFICIENCY
80
70
10k
60
50 1k
40 POWER LOSS
30
20
10
0
0.0001
100
VOUVTIN–
=
=
+48V
–48V
0.001 0.01
FIGURE 16 CIRCUIT 10
0.1 1 10
LOAD CURRENT (A)
3896 TA01b
3896f
1
1 page  
LTC3896
E lectrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are
0V, VDRVSET = 0V, VPRG = FLOAT unless otherwise noted.
aAtlTl Api=n
2v5o°ltCag(Nesotwe i2th),rVesINpe=c1t 2toV,VVORUUT–N,
= 5V with respect
unless otherwise
tnooVteOdU.T–,
EXTVCC
=
SYMBOL
fSYNC
PARAMETER
Low Fixed Frequency
High Fixed Frequency
Synchronizable Frequency
PLLIN Input High Level
PLLIN Input Low Level
CONDITIONS
VFREQ = VOUT–, PLLIN = DC Voltage
VFREQ = INTVCC, PLLIN = DC Voltage
PLLIN = External Clock
PLLIN = External Clock with Respect to GND
PLLIN = External Clock with Respect to GND
MIN
320
485
l 75
l 2.8
l
TYP MAX UNITS
350 380
kHz
535 585
kHz
850 kHz
V
0.5 V
PGOOD Output
VPGL
IPGOOD
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
IPGOOD = 2mA, VPGL with Respect to GND
VPGOOD = 3.3V
VFB with Respect to Set Regulated Voltage
VHFyBstRearemspising Negative
0.02 0.04
10
–13 –10 –7
2.5
V
µA
%
%
VFBVwFiBthRRamesppiencgt
to Set Regulated
Positive
Voltage
Hysteresis
7 10 13
2.5
%
%
Delay for Reporting a Fault
40 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3896 is tested under pulsed load conditions such that TJ ≈
TA. The LTC3896E is guaranteed to meet performance specifications from
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3896I is guaranteed over the
–40°C to 125°C operating junction temperature range and the LTC3896H
is guaranteed over the –40°C to 150°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
and other environmental factors. High temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. The junction temperature (TJ, in °C) is calculated from the
ambient temperature (TA, in °C) and power dissipation (PD, in Watts)
according to the formula:
TJ = TA + (PD • θJA)
where θJA = 28°C/W for the TSSOP package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3896 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB. The specification at 85°C
is not tested in production and is assured by design, characterization and
correlation to production testing at other temperatures (125°C for the
LTC3896E and LTC3896I, 150°C for the LTC3896H). For the LTC3896I
and LTC3896H, the specification at 0°C is note tested in production and is
assured by design, characterization and correlation to production testing
at –40°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current >40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
Note 9: Do not apply a voltage or current source to the NDRV pin, other
than tying NDRV to DRVCC when not used. If used it must be connected
to capacitive loads only (see DRVCC Regulators (OPTI-DRIVE) in the
Applications Information section), otherwise permanent damage may
occur.
Note 10: The minimum input supply (VIN + |VOUT–|) operating range is
dependent on the DRVCC UVLO thresholds as determined by the DRVUV
pin setting.
For more information www.linear.com/LTC3896
3896f
5
5 Page 
LTC3896
Pin Functions
RUN (Pin 34): Run Control Input. Forcing this pin below
1.12V (with respect to GND) shuts down the controller.
Forcing this pin below 0.7V shuts down the entire LTC3896,
reducing quiescent current to approximately 10µA. The
RUN pin is referenced to the GND pin, allowing the LTC3896
to be used with a true ground-referenced external signal
or logic with no level shifters needed. This pin can be tied
to VIN for always-on operation. Do not float this pin.
PHASMD (Pin 36): Control Input to Phase Selector. This
pin determines the CLKOUT phase relationships with
respect to TG. Pulling this pin to VOUT– forces CLKOUT to
be out of phase 90° with respect to TG. Connecting this
pin to INTVCC forces CLKOUT to be out-of-phase 120°
with respect to TG. Floating this pin forces CLKOUT to be
out of phase 180° with respect to TG.
ILIM (Pin 37): Current Comparator Sense Voltage Range
Input. Tying this pin to VOUT– or INTVCC or floating it sets
the maximum current sense threshold to one of three
different levels (50mV, 100mV, and 75mV, respectively).
VINOTUVTC–)C
(Pin
Low
38): Output of the Internal 5V (referenced to
Dropout Regulator. CLKOUT and many of the
low voltage analog and digital circuits are powered from
this voltage source. A low ESR 0.1µF ceramic bypass
capacitor should be connected between INTVCC and VOUT–,
as close as possible to the IC.
For more information www.linear.com/LTC3896
3896f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3896.PDF ] | |
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