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PDF T-51382D064J-FW-P-AA Datasheet ( Hoja de datos )

Número de pieza T-51382D064J-FW-P-AA
Descripción LCD Module
Fabricantes OPTREX 
Logotipo OPTREX Logotipo
Vista previa
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T-51382D064J-FW-P-AA datasheet

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T-51382D064J-FW-P-AA pdf
Note 5-2: R/L is the Right/Left shift signal.
(1) R/L= High, U/D= Low
(2) R/L= Low, U/D= Low
Note 5-3: U/D is the Up/Down shift signal.
(1) R/L= High, U/D= Low
(2) R/L= High, U/D= High
5-2) Backlight driving
Pin No
1
2
3
Symbol
VL1
NC
VL2
Description
Input terminal (Hi voltage side)
No Connection
Input terminal (Low voltage side)
Remark
Note 5-4
Note 5-4: Low voltage side of backlight inverter connects with ground of inverter circuits.
5-3) Input / Output Connector
(A) LCD module connector (Reference)
DF9A-31P-1V
(B) Backlight Connector
JST BHR-03VS-1
Pin No.: 3
Pitch: 4 mm
Red: High Voltage
White: Low Voltage
T-51382D064J-FW-P-AA (AA) No. 2002-0221
OPTREX CORPORATION
Page 5/24

5 Page

T-51382D064J-FW-P-AA arduino
7-5) Horizontal Display Position
Horizontal display position depends on the signal of DENB and the input digital image.
As the rising edge of DENB signal comes, LCD module will create a horizontal sampling
start pulse. At this time, the source driver ICs begin to sample image data and transfer the
digital image data to analogue image data by D/A inverters. Then send the analogue image
signal to the right position of active display area of the LCD panel. If DENB is low, LCD
module will set horizontal display position in default value.
Parameters
DENB Setup Time
Hold Time
Pulse Width
DENB
Horizontal
Keep
Sampling
At Start
“Low” Pulse Position
Hsync-DENB
Phase Difference
Symbol
Tes
Teh
Tepw
Thss
The
Format
All
All
All
VGA-480
VGA-400
VGA-350
Free
Format
All
Min.
10
10
2
128
96
Typ. Max.
Tc-10
Tc-10
640 720
144
144
144
192
160
Unit
ns
ns
clock
clock
clock
clock
clock
clock
Remark
Note 7-4
Note 7-4: In free format condition (Hsync = Positive, Vsync = Positive), if DENB is low, the
position of horizontal sampling start pulse depends on the seven control lines of
HP[6:0] Lattice iSPLSI1032E-LT70 FPGA. The starting position is the count of
{ 128 + Data(HP[6:0]) } clock.
7-6) Vertical Display Position
Mode
VGA-480
VGA-400
VGA-350
Freedom
Mode
Hsync
Negative
Negative
Positive
Positive
Vsync
Negative
Positive
Negative
Positive
V-Start
Position
34
17
30
24
V-Display
480 lines
400 lines
350 lines
480 lines
Remark
Note 7-5
Note 7-6
Note 7-5: As the format is VGA-400 (Hsync = Negative , Vsync = Positive) , LCD module will
adjust the display area to the center of display . At this time , both of the upper and
lower display areas have 40 blanking lines (the display color is black) . The actual
display area is center 400 lines.
T-51382D064J-FW-P-AA (AA) No. 2002-0221
OPTREX CORPORATION
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