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PDF E0C6266 Data sheet ( Hoja de datos )
| Número de pieza | E0C6266 | |
| Descripción | 4-bit Single Chip Microcomputer | |
| Fabricantes | Epson | |
| Logotipo |  |
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PF428-10
E0C6266
4-bit Single Chip Microcomputer
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q Core CPU Architecture
q 38.4kHz/500kHz Twin Clock Operation
q Built-in, 2-ch. Serial Ports
q SVD Circuit/2-ch. Analog Comparators
s DESCRIPTION
The E0C6266 is an advanced single-chip CMOS 4-bit microcomputer consisting of the E0C6200 CMOS 4-bit
core CPU. It also contains the ROM, RAM, 2-channel timer, event counter, start-stop serial ports, clock sync
serial ports and 40 I/O ports.
The E0C6266 provides an excellent solution for low-power consumption systems with clock functions.
s FEATURES
q CMOS LSI 4-bit parallel processing
q Clock ..................................................... 38.4kHz (Typ.)/500kHz (Max.) (selectable by software)
q Instruction set ........................................ 108 instructions
q Instruction cycle time ............................ 130µsec, 182µsec or 312µsec at 38kHz
(depending on instruction)
10µsec, 14µsec or 24µsec at 500kHz
(depending on instruction)
q ROM capacity ....................................... 6,144 × 12 bits
q RAM capacity ........................................ 1,024 × 4 bits
q Input port ............................................... 12 bits
q Output port ............................................ 16 bits
q I/O port .................................................. 12 bits
q Serial I/O port ........................................ 2 ports
• Async; half-duplex, start-stop; transmission speed at 200, 300, 600, 1200, 2400 or 4800 bps;
6 to 8-bit data length; built-in error detect circuit and built-in send/receive buffer register.
• Clock sync.; operating by external clock; start-stop can be set by mask option.
q Built-in time base counter, programmable timer, event counter, and watchdog timer
q Built-in SVD circuit, 2 channels (internal voltage detection)
q Built-in comparator, 2 channels
q Built-in LCD drive power supply, double boosting, external adjustment of output voltage
q Interrupts ............................................... External : Input interrupt
Internal : Timer interrupt
Comparator interrupt
Event counter interrupt
Serial I/O interrupt
3 lines
2 lines (4ch.)
2 lines
1 line
2 lines
q Supply voltage ...................................... 2.2V to 5.5V
q Current consumption ............................ HALT mode (38.4kHz)
: 1.8µA (Typ.)
OPERATING mode (500kHz) : 110µA (Typ.)/150µA (Max.)
q Package ................................................ QFP6-60pin (plastic)
Die form
SEIKO EPSON CORPORATION
1
1 page  
E0C6266
q Analog Circuit Characteristics and Current Consumption
(Unless otherwise specified: VDD=0V, VSS=-2.2 to -5.5V, fOSC1=38.4kHz(crystal), fOSC3=500kHz(ceramic),
Ta=25°C, CG=10pF, CGC/CDC=108pF, VADJ=VL2, RA1/RA2=1MΩ, CS1/CL1–CL4/C1–C3=0.1µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
LCD drive voltage *1
VL1 Connect 1MΩ load resistor between VDD and VL1
0.50
0.45 V
(No panel load), VSS=-2.5 to -5.5V
×VL2
×VL2
VL2 Connect 1MΩ load resistor between VDD and VL2
-2.25
-2.10
-1.95
V
(No panel load), VSS=-2.5 to -5.5V
VL3 Connect 1MΩ load resistor between VDD and VL3
1.50
1.45 V
(No panel load), VSS=-2.5 to -5.5V
×VL2
×VL2
VL4 Connect 1MΩ load resistor between VDD and VL4
2.00
1.95 V
(No panel load), VSS=-2.5 to -5.5V
×VL2
×VL2
BLD voltage (internal)
VBLD1
-2.50
-2.35
-2.20
V
BLD voltage (external)
VBLD2
-1.13
-1.05
-0.97
V
BLD circuit stability time *2 tBLD
100 µS
BLD circuit current
IBLD VSS=-3.0V
10 20 µA
consumption
Analog comparator
VIP Noninverted input (CMPP)
VSS+0.3
-1.0 V
input voltage
VIM Inverted input (CMPM)
Analog comparator
VOF VIP=-1.0 to VSS+0.3V
50 mV
offset voltage
VIM=-1.0 to VSS+0.3V
Analog comparator
tCMP1 VIP=-1.0 to VSS+0.3V
100 µS
stabilizing time *2
VIM=-1.0 to VSS+0.3V
Analog comparator
tCMP2 VSS=-2.2V
100 µS
response time
VIP=-1.1V, VIM=-1.1±0.1V
Analog comparator
ICMP1 VSS=-3.0V
4 10 µA
current consumption (1)
VIP=-1.4V, VIM=-1.6V
Analog comparator
ICMP2 VSS=-3.0V
8 15 µA
current consumption (2)
VIP=-1.6V, VIM=-1.4V
Current consumption
IOP During HALT (1) *3
OSCC="0"
1.8 4.0 µA
During HALT (2) *4
No panel load
1.3 3.0 µA
During operation at 38.4kHz *3
9 15 µA
During operation at 500kHz *5 No panel load
110 150 µA
∗1: When selecting not to use LCD drive power by option, VDD (=0V) is output to VL2.
∗2: The stabilizing time is the time from turning the circuit on until the output data stabilizes.
∗3: The time base counter is RUN status, programmable timer, BLD circuit and analog comparator are OFF status, and the input and
output terminals are static status.
∗4: The same status as ∗1 and is when not using LCD drive power by option, and selecting DC output to the R12 port output form.
∗5: The BLD circuit and analog comparator are OFF status and the input and output terminals are static status.
q Oscillation Characteristics
The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the follow-
ing characteristics as reference values.
OSC1 crystal oscillation circuit
(Unless otherwise specified: VDD=0V, VSS=-2.2 to -5.5V, Crystal: C2-TYPE(Seiko Epson), CG=25pF, CD=built-in, Ta=25°C)
Characteristic
Oscillation start time
Symbol
Condition
tsta VSS=-2.2 to -5.5V
Min.
Typ.
Max.
Unit
3 Sec
Built-in capacitance (drain)
Frequency/voltage deviation
CD For 60 pin plastic package
∂f/∂V VSS=-2.2 to -5.5V
– 20 – pF
5 ppm
Frequency/IC deviation
Frequency adjustment range
Permitted leak resistance
∂f/∂IC
∂f/∂CG CG=5 to 25pF
Rleak Between OSC1 and VDD, VS1
-10 10 ppm
40 ppm
200 MΩ
OSC3 ceramic oscillation circuit
(Unless otherwise specified: VDD=0V, VSS=-2.2 to -5.5V, Ceramic: CSB500E(Murata Mfg. Co.), CGC=CDC=108pF, Ta=25°C)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Oscillation start time
tsta VSS=-2.2 to -5.5V
4 10 mS
5
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