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2Mb Ultra-Low Power Asynchronous CMOS SRAM 128Kx16 bit - ON Semiconductor

Número de pieza N02L63W3A
Descripción 2Mb Ultra-Low Power Asynchronous CMOS SRAM 128Kx16 bit
Fabricantes ON Semiconductor 
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N02L63W3A datasheet

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N02L63W3A pdf
N02L63W3A
Power Savings with Page Mode Operation (WE = VIH)
www.DataSheet4U.com
Page Address (A4 - A16 )
Word Address (A0 - A3)
CE
Word 1
Open page
Word 2
...
Word 16
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Rev. 15 | Page 5 of 11 | www.onsemi.com

5 Page

N02L63W3A arduino
N02L63W3A
www.DataSheet4U.com
Ball Grid Array Package
A1 BALL PAD
CORNER (3)
D
0.28±0.05
1.24±0.10
E
1. 0.35±0.05 DIA.
K TYP
TOP VIEW
SIDE VIEW
2. SEATING PLANE - Z
0.15 Z
0.05 Z
SD
A1 BALL PAD
CORNER
1. DIMENSION IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER.
PARALLEL TO PRIMARY Z.
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
e SPHERICAL CROWNS OF THE
SOLDER BALLS.
SE
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
J TYP
e
BOTTOM VIEW
Dimensions (mm)
DE
6±0.10 8±0.10
SD
0.375
e = 0.75
SE
0.375
J
1.125
K
1.375
BALL
MATRIX
TYPE
FULL
Rev. 15 | Page 10 of 11 | www.onsemi.com

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ON Semiconductor


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