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PDF AD5662 Datasheet ( Hoja de datos )

Número de pieza AD5662
Descripción 2.7 V to 5.5 V 250 uA Rail-to-Rail Output 16-Bit DAC D/A
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5662 datasheet

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AD5662 pdf
Preliminary Technical Data
AD5662www.DataSheet4U.com
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
50 33
13 13
13 13
00
55
4.5 4.5
00
50 33
13 13
00
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to sclk fall ignore
SCLK falling edge to SYNC fall ignore
1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V.
SCLK
SYNC
DIN
t10 t1 t9
t8 t4
t3 t2 t7
DB23
t6
t5
DB0
Figure 2. Serial Write Operation
Rev. PrA | Page 5 of 20

5 Page

AD5662 arduino
Preliminary Technical Data
AD5662www.DataSheet4U.com
Figure 16. Supply Current vs. Logic Input Voltage
Figure 17. Full-Scale Settling Time
Figure 18. Half-Scale Settling Time
Figure 19. Power-On Reset to 0 V
SCLK
2
VOUT
VDD = VREF = 5V
TA = 25°C
EXITS PD TO MIDSCALE
1
CH1 500mV CH2 5.0V
M1.0µs 500MS/s 2.0ns/pt
Figure 20. Exiting Power-Down to Midscale
2.502500
2.502250
2.502000
2.501750
2.501500
2.501250
2.501000
2.500750
2.500500
2.500250
2.500000
2.499750
2.499500
2.499250
2.499000
2.498750
0
VDD = VREF = 5V
TA = 25°C
13nS/SAMPLE NUMBER
1 LSB CHANGE AROUND
MIDSCALE (0x8000 0x7FFF)
GLITCH IMPULSE = 2.723nV.s
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 21. Digital-to-Analog Glitch Impulse (Negative)
Rev. PrA | Page 11 of 20

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