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PDF AD5412 Datasheet ( Hoja de datos )

Número de pieza AD5412
Descripción (AD5412 / AD5422) Current Source & Voltage Output DAC
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AD5412 datasheet

1 Page

AD5412 pdf
Data Sheet
AD5412/AD5422
SPECIFICATIONS
AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
VOLTAGE OUTPUT
Output Voltage Ranges
Accuracy
Resolution
Total Unadjusted Error (TUE)
B Version
A Version
Relative Accuracy (INL)2
Differential Nonlinearity (DNL)
Bipolar Zero Error
Bipolar Zero Error Temperature
Coefficient (TC)3
Zero-Scale Error
Zero-Scale Error TC3
Offset Error
Offset Error TC3
Gain Error
Gain Error TC3
Full-Scale Error
Full-Scale Error TC3
Min
0
0
−5
−10
16
12
−0.1
−0.05
−0.3
−0.1
−0.008
−0.032
−1
−1
−6
−9
−1.5
−5
−8
−3.5
−4
−6
−1.5
−0.07
−0.05
−0.07
−0.05
Typ Max
5
10
+5
+10
±0.01
±0.05
±0.2
±3
+0.1
+0.05
+0.3
+0.1
+0.008
+0.032
+1
+1.3
+6
+9
+1.5
±0.3
±2
±0.2
±2
±0.004
±1
±3
±0.001
±1
±2
+5
+8
+3.5
+4
+6
+1.5
+0.07
+0.05
+0.07
+0.05
Unit Test Conditions/Comments
V
V
V
V
Output unloaded
Bits AD5422
Bits AD5412
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
LSB
LSB
mV
mV
mV
ppm FSR/°C
TA = 25°C
TA = −40°C to +85°C
TA = 25°C
AD5422
AD5412
TA = −40°C to +85°C, guaranteed monotonic
Guaranteed monotonic
TA = −40°C to +85°C, bipolar output range
Bipolar output range
TA = 25°C, bipolar output range
Bipolar output range
mV
mV
mV
ppm FSR/°C
mV
mV
mV
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C, unipolar output range
Unipolar output range
TA = 25°C, unipolar output range
Unipolar output range
TA = 25°C
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C
Rev. M | Page 5 of 44

5 Page

AD5412 arduino
Data Sheet
AD5412/AD5422
Parameter1, 2, 3
READBACK MODE
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
DAISY-CHAIN MODE
t21
t22
t23
t24
t25
t26
t27
t28
t29
Limit at TMIN, TMAX
90
40
40
13
40
5
5
40
35
35
90
40
40
13
40
5
5
40
35
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15 pF)
LATCH rising edge to SDO tristate (CL SDO4 = 15 pF)
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15 pF)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CL SDO = capacitive load on SDO output.
Timing Diagrams
SCLK
LATCH
SDIN
CLEAR
IOUT, VOUT
12
t2
t1
t3
24
t4
t5
t6
DB23
t7
t9
t8
DB0
t10
Figure 2. Write Mode Timing Diagram
Rev. M | Page 11 of 44

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