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PDF 61LV51216 Data sheet ( Hoja de datos )
| Número de pieza | 61LV51216 | |
| Descripción | IS61LV51216 | |
| Fabricantes | Integrated Silicon Solution | |
| Logotipo |  |
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IS61LV51216
ISSI®
512K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
www.datasheet4u.com
MARCH 2005
FEATURES
• High-speed access time:
— 8, 10, and 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
DESCRIPTION
The ISSI IS61LV51216 is a high-speed, 8M-bit static RAM
organized as 525,288 words by 16 bits. It is fabricated using
ISSI's high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields high-performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A data
byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV51216 is packaged in the JEDEC standard
44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE
OE CONTROL
WE CIRCUIT
UB
LB
512K x 16
MEMORY ARRAY
COLUMN I/O
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
1
1 page  
IS61LV51216
ISSI®
CAPACITANCE(1)
Symbol
CIN
www.datasCheOeUtT4u.com
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
8
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
1
2
3
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
AC TEST LOADS
OUTPUT
ZO = 50Ω
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
4
5
6
50Ω
1.5V
30 pF
Including
jig and
scope
3.3V
319 Ω
OUTPUT
5 pF
Including
jig and
scope
353 Ω
7
8
9
10
Figure 1
Figure 2
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
5
5 Page 
IS61LV51216
ISSI®
AC WAVEFORMS
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
www.datasheet4u.com
ADDRESS
OE
CE LOW
t WC
ADDRESS 1
t SA
WE
UB, LB
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t WC
ADDRESS 2
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
1
2
3
4
5
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/10/05
11
11 Page | ||
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