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FSQ0370RNA - Fairchild

Número de pieza Q0370RNA
Descripción FSQ0370RNA
Fabricantes Fairchild 
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Q0370RNA datasheet

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Q0370RNA pdf
Electrical Characteristics
TA = 25°C unless otherwise specified.
Symbol
SenseFET Section(10)
Parameter
IDSS Zero-Gate-Voltage Drain Current
RDS(ON)
Drain-Source
On-State
Resistance(11)
FSQ0170RNA
FSQ0270RNA
FSQ0370RNA
www.DataSheet4U.com
CISS
Input Capacitance
FSQ0170RNA
FSQ0270RNA
FSQ0370RNA
FSQ0170RNA
COSS
Output Capacitance
FSQ0270RNA
FSQ0370RNA
CRSS
Reverse Transfer
Capacitance
FSQ0170RNA
FSQ0270RNA
FSQ0370RNA
FSQ0170RNA
td(on)
Turn-On Delay Time
FSQ0270RNA
FSQ0370RNA
FSQ0170RNA
tr Rise Time
FSQ0270RNA
FSQ0370RNA
FSQ0170RNA
td(off)
Turn-Off Delay Time
FSQ0270RNA
FSQ0370RNA
FSQ0170RNA
tf Fall Time
FSQ0270RNA
FSQ0370RNA
Control Section
fOSC
ΔfOSC
DMAX
DMIN
VSTART
VSTOP
IFB
tS/S
Switching Frequency
Switching Frequency Variation(10)
Maximum Duty Cycle
Minimum Duty Cycle
UVLO Threshold Voltage
Feedback Source Current
Internal Soft-Start Time(10)
Condition
VDS = 700V, VGS = 0V
VDS = 560V, VGS = 0V,
TC = 125°C
VGS = 10V, ID = 0.5A
VGS = 0V, VDS = 25V,
f = 1MHz
VDS = 350V, ID = 1.0A
-25°C TA 85°C
Measured at 0.1 x VDS
VFB = GND
VFB = GND
VFB = GND
VFB = 4V
Min. Typ. Max. Unit
50
200
8.8 11
6.0 7.2
4.0 4.75
250
550
315
25
38
47
10
17
9
12
20
11.2
4
15
34
30
55
28.2
10
25
32
μA
W
pF
ns
92 100 108 KHz
±5 ±10 %
55 60 65 %
0 0 0%
11 12 13
789
V
0.7 0.9 1.1 mA
10 ms
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1
5
www.fairchildsemi.com

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Q0370RNA arduino
4.2 Thermal Shutdown (TSD): The SenseFET and the
control IC are integrated, making it easier for the control
IC to detect the temperature of the SenseFET. When the
temperature exceeds approximately 140°C, thermal
shutdown is activated.
4.3 Over-Voltage Protection (OVP): In the event of a
malfunction in the secondary-side feedback circuit, or an
open feedback loop caused by a soldering defect, the
current through the opto-coupler transistor becomes
almost zero (see Figure 14). VFB climbs up in a similar
manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is activated. Because excess energy
is provided to the output, the output voltage may exceed
www.DataSheet4U.cthome rated voltage before the overload protection is
activated, resulting in the breakdown of the devices in
the secondary side. To prevent this situation, an Over-
Voltage Protection (OVP) circuit is employed. In general,
VCC is proportional to the output voltage and the FPS
uses VCC instead of directly monitoring the output
voltage. If VCC exceeds 19V, the OVP circuit is activated,
resulting in termination of the switching operation. To
avoid undesired activation of OVP during normal
operation, VCC should be designed to be below 19V.
5. Soft-Start: The FPS has an internal soft-start circuit
that slowly increases the SenseFET current after start-
up, as shown in Figure 16. The typical soft-start time is
10ms, where progressive increments of the SenseFET
current are allowed during the start-up phase. The pulse
width to the power switching device is progressively
increased to establish the correct working conditions for
transformers, inductors, and capacitors. The voltage on
the output capacitors is progressively increased to
smoothly establish the required output voltage. This also
helps prevent transformer saturation and reduces the
stress on the secondary diode during startup.
5V #6,7,8
DRAIN
ILIM Rsense
#1
GND
FSQ0x70RNA Rev. 1.00
Figure 16. Soft-Start Function
6. Burst Operation: To minimize power dissipation in
standby mode, the FPS enters burst-mode operation.
Feedback voltage decreases as the load decreases, as
shown in Figure 17, and the device automatically enters
burst-mode when the feedback voltage drops below
VBURH (typically 600mV). Switching continues until the
feedback voltage drops below VBURL (typically 400mV).
At this point, switching stops and the output voltage
starts to drop at a rate dependent on the standby current
load. This causes the feedback voltage to rise. Once it
passes VBURH, switching resumes. The feedback
voltage then falls and the process is repeated. Burst-
mode operation alternately enables and disables
switching of the SenseFET and reduces switching loss in
standby mode.
Burst Operation
Burst Operation
VFB
Normal
Operation
VBURH
VBURL
Current
Waveform
Switching OFF
Switching
OFF
FSQ0x70RNA Rev.00
Figure 17. Burst Operation Function
7. Adjusting Peak Current Limit: As shown in Figure
18, a combined 2.8kΩ internal resistance is connected to
the non-inverting lead on the PWM comparator. An
external resistance of Rx on the current limit pin forms a
parallel resistance with the 2.8kΩ when the internal
diodes are biased by the main current source of 900µA.
VCC
VFB IDELAY
3
5μA
VCC
900μA
IFB
2k
PWM
Comparator
IPK
4
Rx
0.8k
SenseFET
Current
Sense
FSQ0x70RNA Rev. 1.00
Figure 18. Peak Current Limit Adjustment
For example, FSQ0270RNA has a typical SenseFET
peak current limit (ILIM) of 0.9A. ILIM can be adjusted to
0.6A by inserting Rx between the IPK pin and the ground.
The value of the Rx can be estimated by the following
equations:
0.9A: 0.6A = 2.8kΩ : XkΩ,
X = Rx || 2.8kΩ
where X represents the resistance of the parallel network.
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA, FSQ0370RNA Rev. 1.0.1
10
www.fairchildsemi.com

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