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Dual 16-Bit nanoDAC - Analog Devices

Número de pieza AD5663
Descripción Dual 16-Bit nanoDAC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5663 datasheet

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AD5663 pdf
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1
Table 4.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
9
9
13
5
5
0
15
13
0
10
15
5
0
300
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
1 Guaranteed by design and characterization; not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
SCLK
SYNC
DIN
LDAC1
t10
t8 t4
DB23
t6
t5
LDAC2
CLR
t13
VOUT
t15
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t1
t3 t2
t9
t7
DB0
t14
t11
t12
Figure 2. Serial Write Operation
AD5663
Rev. 0 | Page 5 of 24

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AD5663 arduino
AD5663
VDD = VREF = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2k
AND 200pF TO GND
VOUT = 909mV/DIV
1
TIME BASE = 4µs/DIV
Figure 16. Full-Scale Settling Time, 5 V
VDD = VREF = 5V
TA = 25°C
VDD
1
2
VOUT
MAX(C2)*
420.0mV
CH1 2.0V
CH2 500mV
M100µs 125MS/s
A CH1 1.28V
Figure 17. Power-On Reset to 0 V
8.0ns/pt
SYNC
1
SLCK
3
VOUT
VDD = 5V
2
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
Figure 18. Exiting Power-Down to Midscale
1.4V
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
0
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
50 100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 19. Digital-to-Analog Glitch Impulse (Negative)
2.498
2.497
2.496
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
2.495
2.494
2.493
2.492
2.491
0
50 100 150 200 250 300 350 400 450
SAMPLE NUMBER
Figure 20. Analog Crosstalk
512
–20
VDD = 5V
–30
TA = 25°C
DAC LOADED WITH FULL SCALE
VREF = 2V ± 0.3V p-p
–40
–50
–60
–70
–80
–90
–100
2k 4k 6k 8k 10k
FREQUENCY (Hz)
Figure 21. Total Harmonic Distortion
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