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PDF AD5664 Datasheet ( Hoja de datos )

Número de pieza AD5664
Descripción (AD5624 / AD5664) nanoDACs
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5664 datasheet

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AD5664 pdf
AD5624/AD5664
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
9
9
13
5
5
0
15
13
0
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
SCLK
SYNC
DIN
t10
t8
t4
DB23
t6
t5
t1
t3 t2
t9
t7
DB0
Figure 2. Serial Write Operation
Rev. 0 | Page 5 of 24

5 Page

AD5664 arduino
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
0
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
50 100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 22. Digital-to-Analog Glitch Impulse (Negative)
2.498
2.497
2.496
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
2.495
2.494
2.493
2.492
2.491
0
50 100 150 200 250 300 350 400 450
SAMPLE NUMBER
Figure 23. Analog Crosstalk
–20
VDD = 5V
–30
TA = 25°C
DAC LOADED WITH FULL SCALE
–40 VREF = 2V ± 0.3V p-p
512
–50
–60
–70
–80
–90
–100
2k 4k 6k 8k
(Hz)
Figure 24. Total Harmonic Distortion
10k
AD5624/AD5664
16
VREF = VDD
TA = 25°C
14
12
VDD = 3V
10
8 VDD = 5V
6
4
0 1 2 3 4 5 6 7 8 9 10
CAPACITANCE (nF)
Figure 25. Settling Time vs. Capacitive Load
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
1
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
Figure 26. 0.1 Hz to 10 Hz Output Noise Plot
800
VDD = VREF = 5V
700 TA = 25°C
600
500
400
300
200
100
0
10
100 1k 10k 100k
FREQUENCY (Hz)
Figure 27. Noise Spectral Density
1M
Rev. 0 | Page 11 of 24

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