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PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2 - Q-67106-H6514 - Siemens Semiconductor Group

Número de pieza Q-67106-H6514
Descripción PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2
Fabricantes Siemens Semiconductor Group 
Logotipo Siemens Semiconductor Group Logotipo
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Q-67106-H6514 datasheet

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Semiconductor Group
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The circuit consists of a reference-, a- and n-counter, a dual modulus control logic, a
phase detector with charge pump output and a serial control logic. The setting of the
operating mode and the selection of the counter ratios is done serially at the ports CLK,
DA and EN.
The operating modes allow the selection of single or dual operation, asynchronous or
synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PD-
output current modes, polarity setting of the PD-output signal, adjustment of the trigger-
edge of the MOD-output signal, 2 standby modes and the control of the multifunction
outputs MFO1 and MFO2.
The reference frequency is applied at the RI-input and scaled down by the r-counter. It’s
maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and scaled
down by the n- or n/a-counter according to single or dual mode operation. The maximum
value at FI is 220 MHz at single-, and 65 MHz at dual mode operation.
The phase and frequency sensitive phase detector produces an output signal with
adjustable anti-backlash impulses in order to prevent a dead zone for very small phase
deviations. Phase differences of less than 100 ps can be resolved. In general the
shortest anti-backlash pulse gives the best system performance.
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Programming of the IC is done by a serial data control. The contents of the message are
assigned to the functional units according to the address. 6LQJOH RU GXDO PRGH
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The PMB 2306T offers the possibility of synchronous data acquisition to avoid error
signals at the phase detector due to non-corresponding dividing factors in the counters
produced by asynchronous loading.
Synchronous programming guarantees control during changes of frequency or channel.
That means that the state of the phase detector or the phase difference is kept
maintained, and in case of “lock in”, the control process starts with the phase difference
“zero”.
Semiconductor Group
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