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PDF 7013 Data sheet ( Hoja de datos )

Número de pieza 7013
Descripción CMOS TIA IS-54 Baseband Receive Port
Fabricantes Analog Devices 
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a
CMOS
TIA IS-54 Baseband Receive Port
AD7013
FEATURES
Single +5 V Supply
Receive Channel
Differential or Single-Ended Analog Inputs
Auxiliary Set of Analog I & Q Inputs
Two Sigma-Delta A/D Converters
Choice of Two Digital FIR Filters
Root-Raised-Cosine Rx Filters, α = 0.35
Brick Wall FIR Rx Filters
On-Chip or User Rx Offset Calibration
ADC Sampling Vernier
Three Auxiliary DACs
On-Chip Voltage Reference
Low Active Power Dissipation, Typical 45 mW
Low Sleep Mode Power Dissipation, <50 µW
28-Pin SSOP
APPLICATIONS
American TIA Digital Cellular Telephony
American Analog Cellular Telephony
Digital Baseband Receivers
GENERAL DESCRIPTION
The AD7013 is a complete low power, CMOS, TIA IS-54 base-
band receive port with single +5 V power supply. The part is
designed to perform the baseband conversion of I and Q
waveforms in accordance with the American (TIA IS-54)
Digital Cellular Telephone system.
The receive path consists of two high performance sigma-delta
ADCs, each followed by a FIR digital filter. A primary and
auxiliary set of IQ differential analog inputs are provided,
where either can be selected as inputs to the sigma-delta
ADCs. Also, a choice of two frequency responses are available
for the receive FIR filters; a Root-Raised-Cosine filter for
digital mode or a brick wall response for analog mode.
Differential analog inputs are provided for both I and Q
channels. On-chip calibration logic is also provided to remove
either on-chip offsets or remove system offsets. A 16-bit serial
interface is provided, interfacing easily to most DSPs. The
receive path also provides a means to vary the sampling
instant, giving a resolution to 1/32 of a symbol interval.
The auxiliary section provides two 8-bit DACs and one 10-bit
DAC for functions such as automatic gain control (AGC),
automatic frequency control (AFC) and power amplifier
control.
As it is a necessity for all digital mobile systems to use the
lowest possible power, the device has receive and auxiliary
power down options. The AD7013 is housed in a space
efficient 28-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
DxCLK
DATA IN
FRAME IN
MODE1
FRAME OUT
Rx CLK
Rx DATA
Rx FRAME
MCLK
DGND VDD
AUX DAC1 AUX DAC2 AUX DAC3
FS ADJUST VAA AGND
SERIAL
INTERFACE
RECEIVE
CHANNEL
SERIAL
INTERFACE
10-BIT
AUX DAC
8-BIT
AUX DAC
8-BIT
AUX DAC
FULL-SCALE
ADJUST
LATCH
LATCH
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
LATCH
1.23V
REFERENCE
AD7013
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
AGND
AGND
BYPASS
IRx
IRx
AUX IRx
AUX IRx
QRx
QRx
AUX QRx
AUX QRx
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

1 page




7013 pdf
SSOP Pin
Number
Mnemonic
POWER SUPPLY
1 VAA
21 VDD
10, 25, 27
16
AGND
DGND
ANALOG SIGNAL AND REFERENCE
28 BYPASS
2, 4 IRx, IRx
6, 8 QRx, QRx
3, 5 AUX IRx, AUX IRx
7, 9 AUX QRx, AUX QRx
24
3, 22
26
AUX DAC1
AUX DAC2, AUX DAC3
FS ADJUST
SERIAL INTERFACE AND CONTROL
20 MCLK
19 DxCLK
17 FRAME IN
18 DATA IN
15 FRAME OUT
11 MODE1
RECEIVE INTERFACE AND CONTROL
14 RxCLK
12 RxFRAME
13 RxDATA
PIN FUNCTION DESCRIPTIONS
AD7013
Function
Positive Power Supply for Analog section. A 0.1 µF decoupling capacitor should be
connected between this pin and AGND.
Positive Power Supply for Digital section. A 0.1 µF decoupling capacitor should be
connected between this pin and DGND. Both VAA and VDD should be externally
tied together.
Analog Ground.
Digital Ground. Both AGND and DGND should be externally tied together.
Reference Decoupling Output. A 10 nF decoupling capacitor should be connected
between this pin and AGND.
Differential Analog Inputs for the I receive channel. These are the primary receive
analog inputs and are selected by setting CR12 to a zero in the command register.
Differential Analog Inputs for the Q receive channel. These are the primary receive
analog inputs and are selected by setting CR12 to a zero in the command register.
Auxiliary Differential Analog Inputs for the I receive channel. The Auxiliary inputs
are selected by setting CR12 to a one in the command register.
Auxiliary Differential Analog Inputs for the Q receive channel. The Auxiliary inputs
are selected by setting CR12 to a one in the command register.
Analog output from the 10-bit auxiliary DAC.
Analog outputs from the 8-bit auxiliary DACs.
An external resistor is connected from this pin to ground to determine the full-
scale current for AUX DAC1, AUX DAC2, and AUX DAC3.
Master Clock, Digital Input. When operating in IS-54 Digital mode this pin should
be driven by a 6.2208 MHz CMOS compatible clock source and 5.12 MHz clock
source for Analog Mode.
Transmit Clock, Digital Output. This is a continuous clock equal to MCLK/2 which
can be used to clock the serial port of a DSP.
Digital Input. This is used to frame the clocking in of 16-bit words for the control
registers serial interface.
Digital Input. Transmit Serial Data, digital input. This pin is used to clock in
data for the serial interface on the rising edge of DxCLK.
Digital Output. This output represents a buffered version of FRAME IN and is
controlled by the MODE1 pin. This pin can be used to daisy chain the
FRAME IN signal.
Digital Input. This pin determines the state of FRAME OUT. When MODE1 is high,
FRAME IN is buffered and made available on FRAME OUT.
When MODE1 is low, FRAME OUT is in 3-STATE.
Output Clock for the receive section interface.
Synchronization output for framing I and Q data at the receive interface.
Receive Data, digital output. I and Q data are available at this pin via a 16-bit serial
interface. Data is valid on the falling edge of RxCLK. I and Q data are clocked out
as two 16-bits words, with the I word being clocked first. The last bit in each 16-bit
word is a I/Q flag bit, indicating whether that word is an I word or a Q word.
REV. A
–5–

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7013 arduino
AD7013
RECEIVE SECTION
The receive section consists of I and Q receive channels, each
comprising of a simple switched-capacitor filter followed by a 15-bit
sigma-delta ADC. The data is available on a 16-bit serial interface,
interfacing easily to most DSPs. On-board digital filters, which
form part of the sigma-delta ADCs, also perform system level
filtering. A choice of two digital filter responses are available,
optimized for either π/4 DQPSK digital mode or the existing analog
cellular system. For digital mode, Root-Raised Cosine digital filters
can be selected; whereas for analog mode, digital filters with a
–3 dB point of 11.4 kHz can be selected. Their amplitude and
phase response characteristics provide excellent adjacent channel
rejection. A means is also provided to calibrate either on-chip or
receive path offsets in both the I and Q channels. The receive
section is also provided with a low power sleep mode, drawing only
minimal current between receive bursts.
Switched Capacitor Input
The receive section analog front-end is sampled at MCLK/4 by a
switched-capacitor filter. The filter has a zero at MCLK/8 as
shown in Figure 8a. The receive channel also contains a digital
low-pass filter (further details are contained in the following
section) which operates at a clock frequency of MCLK/8. Due to
the sampling nature of the digital filter, the pass band is repeated
about the operating clock frequency (MCLK/8) and at multiples of
the clock frequency (Figure 8b). Because the first null of the
switched-capacitor filter coincides with the first image of the digital
filter, this image is attenuated by an additional 30 dBs (Figure 8c)
further simplifying the external antialiasing requirements. A simple
R-C Network can be used to attenuate the digital filter image at
MCLK/8 as shown in Figure 9.
0dBs
FRONT-END
ANALOG
FILTER
TRANSFER
MCLK/8
a.
MCLK/4
MCLK/2
MHz
Receive Channel Differential Inputs
The receive channel uses differential inputs to interface more easily
to IQ demodulators and also to provide common-mode noise
rejection. However, if required the receive channel inputs can also
be configured for single ended operation. The primary and
auxiliary channels have similar performance and either can be used
for differential operation or single-ended operation. The CR12
control bit determines whether the primary or auxiliary inputs are
connected to the differential inputs of the sigma-delta modulator.
Figure 9 illustrates an antialiasing filter comprised of a single pole
RC network with a –3 dB frequency of 159 kHz. The low-pass
filter provides sufficient rejection at images of the FIR digital filter
illustrated in Figure 10c.
For single ended operation, the inverting input should be con-
nected to a bias voltage and the noninverting input should swing
± 1.3 V around this bias voltage in order to exercise the entire ADC
range. In applications where the full ± 1.3 V range is not required,
the on-chip 1.23 V reference can be used to provide the bias
voltage. For instance as in Figure 10, an OP295 rail-to-rail low
power op amp is used to buffer the BYPASS pin in order to
generate a 1.23 VBIAS. The VBIAS is connected to the inverting input
thereby setting the single-ended input range equal to 0 V to 2.46 V.
Also with the addition of an attenuator circuit the input range can
be expanded to 0 V to 4.92 V as shown on the second ADC
channel. If the inverting input is tied to AGND, then only half the
ADC range is available.
IRx
AD7013
IR x
0.01nF
QRx
QRx
BYPASS
0.01nF
5k
5k
I
IQ
DEMODULATOR
T
5k
Q
5k
Q
10nF
0dBs
DIGITAL
FILTER
TRANSFER
FUNCTION
MCLK/8
b.
MCLK/4
MCLK/2
MHz
0dBs
SYSTEM
FILTER
TRANSFER
FUNCTION
–30
dBs
MAX
MCLK/8
MCLK/4
MCLK/2
MHz
c.
Figure 8. Switched Capacitor and Digital Filter Transfer
Functions
Figure 9. External RC Network for Differential Signals
AUX IRx
AUX IRx
AD7013
AUX QRx
AUX QRx
BYPASS
10k
0.1nF
0 TO 2.46 VOLTS
0.1nF
10k
10k0 TO 4.92 VOLTS
10nF
5V
295
1.23 VOLTS
Figure 10. External RC Network for Single-Ended Signals
REV. A
–11–

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