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PDF 6052AH Datasheet ( Hoja de datos )

Número de pieza 6052AH
Descripción MCS51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo

Total 21 Páginas
		
6052AH Hoja de datos, Descripción, Manual
smu @
MCS@51
8-BIT CONTROL-ORIENTED MICROCONTROLLERS
Commercial/Express
8031AH18051AH18051AHP
8032N+18052N-I
8751W8751H-8
8751BW8752BI-I
s High Performance HMOS Process
s Boolean Processor
s Internal Timers/Event Counters
s Bit-Addressable RAM
s 2-Level interrupt Priority Structure
s 32 1/0 Lines (Four 8-Bit Ports)
s 64K External Program Memory Space
s Security Feature Protects EPROM Parts
Against Software Piracy
s Programmable Full Duplex Serial
Channel
s 111 Instructions (64 Single-Cycle)
s 64K External Data Memory Space
s Extended Temperature Range
(–40”C to +85”C)
The MCS@51 controllers are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc-
tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can
be erased with ultraviolet light. His fully compatible with the 8051AH but incorporates one additional feature: a
Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The
8751 H-8 is identical to the 8751 H but only operates up to 8 MHz.
The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.
The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is
fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this
table for the ROM, ROMless and-EPROM versions of each product.
Device
8031AH
8051AH
6051AHP
8751 H
8751 H-8
6751 BH
8032AH
6052AH
8752BH
Intsrnal Memory
Program
Data
none
4K X 8 ROM
4K X 6 ROM
4K X 8 EPROM
4K X 8 EPROM
4K X 8 EPROM
none
8K X 8 ROM
8K X 8 EPROM
128 X 8 RAM
128 X 8 RAM
128 X 8 RAM
128 X 8 RAM
128 X 6 RAM
128 X 8 RAM
256 X 6 RAM
256 X 8 RAM
256 X 8 RAM
Timera/
Event Counters
2 x 18-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
3 x 16-Bit
3 x 16-Bit
3 x 16-Bit
Interrupts
5
5
5
5
5
5
6
6
6
I Intel Corporationassumes no responsibilityfor the use of any circuit~ other than circuitryembodied in an Intel product.No other circuitpatent
licenses are implied.Informationcontained herein supersedes previouslypublishedspecificationson theaa davices from Intel.
O INTEL CORPORATION, 1994
October 1994
Order Numben 272318-002

1 page

6052AH pdf
w
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the device is executing code from external
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
skipped during each access to external Data Memo-
ry
~/Vpp: External Access enable ~ must be
strapped to VSS in order to enable any MCS 51 de-
vice to fetch code from external Program memory
locations starting at OOOOHup to FFFFH. ~ must
be strapped to VCCfor internal program execution.
Note, however, that if the Security Bit in the EPROM
devices is programmed, the device will not fetch
code from any location in external Program Memory.
This pin also receives the programming supply volt-
age (VPP) during programming of the EPROM parts.
MCS” 51 CONTROLLER
To drive the device from an external clock source,
XTAL1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTAL1
Vss
C2 I
Eln
cl
XTAL2
XTAL1
Vss
=
272318-3
Cl, C2 = 30 PF +10 PF for Crystals
For Ceramic Resonators contact resonatormanufacturer.
Figure 3. Oscillator Connections
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifi-
er,
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155; “Oscillators for Microcontrol-
Iers,” Order No, 230659.
272318-4
Figure 4. External Drive Configuration
EXPRESS Version
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS 51 family
of microcontrollers. These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
standards.
The EXPRESS program includes the commercial
standard temperature range with burn-in, and an ex-
tended temperature range with or without burn-in.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
temperature range of O“C to + 70”C. With the ex-
tended temperature range option, operational char-
acteristics are guaranteed over a range of –40”C to
+ 85”C.
The optional burn-in is dynamic, for a minimum time
of 160 hours at 125°C with VCC = 5.5V * 0.25V,
following guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESSversions are identified
by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this
data sheet specifies the parameters which deviate
from their commercial temperature range limits.
I5

5 Page

6052AH arduino
MCS@51 CONTROLLER
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PSEN
PORT O
w--- TLHLL _
\,
TLLPL- ~
-TAVLL+
+
TLLIV
/
TLLAX
TPLPH
/
PORT 2
x1
AO-A15
x
\
A8 -A15
272318-5
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
m
PORTO
PORT2
+TLHLL+
Y
‘LLOv ~
— TLLWL
TRLRH –—
+ TAVLL +
_TLLAX
b
—TRLDV4
i‘
TRHOX+
AO-A7 FROM RI OR OPL
OATA IN
.
.
TAVOV
b
x r P2.O-P2.7 OR A8-A15 FROMDPH
TWHLH
\
/
x A8-A15 FROMPCH
272318-6
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
m
WT
PORTO
PORT2
\,
TLHLL—
‘TLLwL~TwLwH
1 7t=-TAVLL
+TLLAX
TQVWX k
II I
AO-A7
FROMRIOR OPL M
TQVWH
OATAOUT
xI
P2.O-P2.7 OR A8-A15 FROMOPH
TWHLH
\
*
/
/
1‘
TWHQX
:r
xx1
AO-A7 FROMFCL
x A8-A15 FROMPCH
272318-7
11

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