PDF M-8888 Datasheet ( Hoja de datos )

Número de pieza M-8888
Descripción DTMF Transceiver
Fabricantes Clare Inc. 
Logotipo Clare  Inc. Logotipo
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M-8888 datasheet

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M-8888 pdf
The divider output clocks another counter that
addresses the sinewave lookup ROM. The lookup
table contains codes used by the switched capacitor
D/A converter to obtain discrete and highly accurate
DC voltage levels. Two identical circuits are used to
produce row and column tones, which are then mixed
using a low-noise summing amplifier. The oscillator
described needs no startup time as in other DTMF
generators, since the crystal oscillator is running con-
tinuously, thus providing a high degree of tone burst
accuracy. When there is no tone output signal, the
TONE pin assumes a DC level of 2.5 volts (typically).
A bandwidth limiting filter is incorporated to attenuate
distortion products above 4 KHz.
Burst Mode:
Certain telephony applications require that generated
DTMF signals be of a specific duration, determined
Actual Frequencies vs Standard Requirements
Active Cell
Output Frequency(Hz)
697 699.1
770 766.2
852 847.4
941 948.0
% Error
+ 0.30
- 0.49
- 0.54
+ 0.74
+ 0.57
- 0.32
- 0.35
+ 0.73
Control Register A Description
either by the application or by any of the existing
exchange transmitter specifications. Standard DTMF
signal timing can be accomplished by making use of
the burst mode. The transmitter is capable of issuing
symmetric bursts/pauses of predetermined duration.
This burst/pause duration is 51 ms ± 1 ms, a standard
interval for autodialer and central office applications.
After the burst/pause has been issued, the appropriate
bit is set in the status register, indicating that the trans-
mitter is ready for more data.
The timing described in the previous paragraph is
available when the DTMF mode has been selected.
However, when call progress (CP) mode is selected, a
secondary burst/pause time is available that extends
this interval to 102 ms ± 2 ms. The extended interval is
useful when precise tone bursts of longer than 51 ms
duration and 51 ms pause are desired. Note that when
CP mode and burst mode have been selected, DTMF
tones may be transmitted only and not received. In
applications where a nonstandard burst/pause time is
desirable, a software timing loop or external timer can
be used to provide the timing pulses when the burst
mode is disabled by enabling and disabling the trans-
The M-8888 is initialized on powerup sequence with
DTMF mode and burst mode selected.
Single-Tone Generation:
A single-tone mode is available whereby individual
tones from the low group or high group can be gener-
ated. This mode can be used for DTMF test equipment
applications, acknowledgment tone generation, and
distortion measurements. Refer to the Control Register
B Description below for details.
Bit Name Function Description
Tone output A logic 1 enables the tone output. This function can be implemented in either the burst
mode or nonburst mode.
b1 CP/DTMF Mode control
In DTMF mode (logic 0), the device is capable of generating and receiving DTMF signals.
When the call progress (CP) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow
call progress tones to be detected. Call progress tones within the specified bandwidth will be presented
at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (b2 = 1). Also, when the
CP mode and burst mode have both been selected, the transmitter will issue DTMF signals with a burst
and pause of 102 ms (typ) duration. This signal duration is twice that obtained from the DTMF transmit-
ter, if DTMF mode had been selected. Note that DTMF signals cannot be decoded when the CP mode
has been selected.
b2 IRQ Interrupt enable A logic 1 enables the interrupt mode. When this mode is active and the DTMF mode has
been selected (b1 = 0), the IRQ/CP pin will pull to a logic 0 condition when either (1) a valid DTMF sig-
nal has been received and has been present for the guard time or (2) the transmitter is ready for more
data (burst mode only).
b3 RSEL Register select A logic 1 selects control register B on the next write cycle to the control register address. Subsequent
write cycles to the control register are directed back to control register A.
Rev. 1

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M-8888 arduino
Test Loads
Timing Diagrams
Rev. 1

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