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PDF AD5552 Data sheet ( Hoja de datos )

Número de pieza AD5552
Descripción 5 V/ Serial-Input Voltage-Output/ 14-Bit DACs
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
5 V, Serial-Input
Voltage-Output, 14-Bit DACs
AD5551/AD5552
FEATURES
Full 14-Bit Performance
5 V Single Supply Operation
Low Power
Fast Settling Time
Unbuffered Voltage Output Capable of Driving 60 k
Loads Directly
SPI™/QSPI™/MICROWIRE™-Compatible Interface
Standards
Power-On Reset Clears DAC Output to 0 V (Unipolar
Mode)
Schmitt Trigger Inputs for Direct Optocoupler Interface
APPLICATIONS
Digital Gain and Offset Adjustment
Automatic Test Equipment
Data Acquisition Systems
Industrial Process Control
GENERAL DESCRIPTION
The AD5551 and AD5552 are single, 14-bit, serial input, voltage
output DACs that operate from a single 5 V ± 10% supply.
The AD5551 and AD5552 utilize a versatile 3-wire interface that
is compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards.
These DACs provide 14-bit performance without any adjust-
ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed by an output buffer.
With an external op amp the AD5552 can be operated in bipo-
lar mode generating a ± VREF output swing. The AD5552 also
includes Kelvin sense connections for the reference and analog
ground pins to reduce layout sensitivity. For higher precision
applications, please refer to 16-bit DACs AD5541, AD5542,
and AD5544.
The AD5551 and AD5552 are available in an SO package.
FUNCTIONAL BLOCK DIAGRAMS
VREF
AD5551
VDD
14-BIT DAC
VOUT
CS
DIN
SCLK
CONTROL
LOGIC
14-BIT DATA LATCH
SERIAL INPUT REGISTER
AGND
DGND
VREFF
VREFS
CS
LDAC
SCLK
DIN
AD5552
RINV
CONTROL
LOGIC
VDD
RFB
14-BIT DAC
14-BIT DATA LATCH
SERIAL INPUT REGISTER
RFB
INV
VOUT
AGNDF
AGNDS
DGND
PRODUCT HIGHLIGHTS
1. Single Supply Operation.
The AD5551 and AD5552 are fully specified and guaranteed
for a single 5 V ± 10% supply.
2. Low Power Consumption.
Typically 1.5 mW with a 5 V supply.
3. 3-Wire Serial Interface.
4. Unbuffered output capable of driving 60 kloads, which
reduces power consumption as there is no internal buffer
to drive.
5. Power-On Reset Circuitry.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

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AD5552 pdf
AD5551/AD5552
Mnemonic
RFB
VOUT
AGNDF
AGNDS
VREFS
VREFF
CS
SCLK
NC
DIN
LDAC
DGND
INV
VDD
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD5552 PIN FUNCTION DESCRIPTIONS
Description
Feedback Resistor. In bipolar mode connect this pin to external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from
2 V to VDD.
This is the voltage reference input (force) for the DAC. Connect to external reference ranges
from 2 V to VDD.
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
No Connect.
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on
the rising edge of SCLK.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with
the contents of the input register.
Digital Ground. Ground reference for digital circuitry.
Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps
inverting input in bipolar mode.
Analog Supply Voltage, 5 V ± 10%.
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in TPC 1.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maximum
ensures monotonicity. TPC 4 illustrates a typical DNL versus
code plot.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/°C.
Zero Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition. A plot of the glitch impulse is shown
in TPC 14.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. CS is
held high, while the CLK and DIN signals are toggled. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa. A typi-
cal plot of digital feedthrough is shown in TPC 13.
Power Supply Rejection Ratio
This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power-supply rejection
ratio is quoted in terms of % change in output per % change in
VDD for full-scale output of the DAC. VDD is varied by ± 10%.
Reference Feedthrough
This is a measure of the feedthrough from the VREF input to the
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in mV p-p.
REV. 0
–5–

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AD5552 arduino
AD5551/AD5552
The 80C51/80L51 provides the LSB first, while the AD5551/
AD5552 expects the MSB of the 14-bit word first. Care should be
taken to ensure the transmit routine takes this into account.
Usually it can be done through software by shifting out and accu-
mulating the bits in the correct order before inputting to the DAC.
Also, 80C51 outputs 2 byte words/16 bits data, thus the first two
bits, after rearrangement, should be DON’T CARE as they will
be dropped from the DAC’s 14-bit word.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock must
be inverted as the DAC clocks data into the input shift register on
the rising edge of the serial clock. The 80C51/80L51 transmits
its data in 8-bit bytes with only eight falling clock edges occur-
ring in the transmit cycle. As the DAC requires a 14-bit word,
P3.3 (or any one of the other programmable bits) is the CS input
signal to the DAC, so P3.3 should be brought low at the begin-
ning of the 16-bit write cycle 2 × 8 bit words and held low until
the 16-bit 2 × 8 cycle is completed. After that, P3.3 is brought
high again and the new data loads to the DAC. Again, the first
two bits, after rearranging, should be DON’T CARE. LDAC
on the AD5552 may also be controlled by the 80C51/80L51 serial
port output by using another bit programmable pin, P3.4.
APPLICATIONS
Optocoupler interface
The digital inputs of the AD5551/AD5552 are Schmitt-
triggered, so they can accept slow transitions on the digital input
lines. This makes these parts ideal for industrial applications
where it may be necessary that the DAC is isolated from the
controller via optocouplers. Figure 9 illustrates such an interface.
POWER
5V
REGULATOR
10F
0.1F
Decoding Multiple AD5551/AD5552s
The CS pin of the AD5551/AD5552 can be used to select one
of a number of DACs. All devices receive the same serial clock
and serial data, but only one device will receive the CS signal at
any one time. The DAC addressed will be determined by the
decoder. There will be some digital feedthrough from the digital
input lines. Using a burst clock will minimize the effects of digi-
tal feedthrough on the analog signal channels. Figure 10 shows a
typical circuit.
SCLK
DIN
VDD
AD5551/AD5552
CS
VOUT
DIN
SCLK
ENABLE
CODED
ADDRESS
EN
DECODER
DGND
AD5551/AD5552
CS
VOUT
DIN
SCLK
AD5551/AD5552
CS
VOUT
DIN
SCLK
AD5551/AD5552
CS
DIN
SCLK
VOUT
Figure 10. Addressing Multiple AD5551/AD5552s
SCLK
VDD
10k
SCLK
VDD
VDD
AD5551/AD5552
10k
CS CS VOUT
VDD
10k
DIN DIN
GND
Figure 9. AD5551/AD5552 in an Optocoupler Interface
REV. 0
–11–

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