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5 V/ Serial-Input Voltage-Output/ 16-Bit DACs - Analog Devices

Número de pieza AD5542
Descripción 5 V/ Serial-Input Voltage-Output/ 16-Bit DACs
Fabricantes Analog Devices 
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AD5542 datasheet

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AD5542 pdf
Mnemonic
VOUT
AGND
REF
CS
SCLK
DIN
DGND
VDD
Pin No.
1
2
3
4
5
6
7
8
AD5541/AD5542
AD5541 PIN FUNCTION DESCRIPTIONS
Description
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry.
This is the voltage reference input for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to VDD.
This is a logic input signal. The chip select signal is used to frame the serial data input.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on
the rising edge of SCLK.
Digital Ground. Ground reference for digital circuitry.
Analog Supply Voltage, 5 V ± 10%.
AD5541 PIN CONFIGURATION
SOIC
AD5542 PIN CONFIGURATION
SOIC
VOUT 1
8 VDD
AGND 2 AD5541 7 DGND
TOP VIEW
REF 3 (Not to Scale) 6 DIN
CS 4
5 SCLK
RFB 1
14 VDD
VOUT 2
13 INV
AGNDF
AGNDS
REFS
3 12 DGND
AD5542
4 TOP VIEW 11 LDAC
5 (Not to Scale) 10 DIN
REFF 6
CS 7
9 NC
8 SCLK
NC = NO CONNECT
Mnemonic
RFB
VOUT
AGNDF
AGNDS
REFS
REFF
CS
SCLK
NC
DIN
LDAC
DGND
INV
VDD
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD5542 PIN FUNCTION DESCRIPTIONS
Description
Feedback Resistor. In bipolar mode connect this pin to external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
This is the voltage reference input (sense) for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to VDD.
This is the voltage reference input (force) for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to VDD.
This is a logic input signal. The chip select signal is used to frame the serial data input.
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
No Connect.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on
the rising edge of SCLK.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with
the contents of the input register.
Digital Ground. Ground reference for digital circuitry.
Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps
inverting input in bipolar mode.
Analog Supply Voltage, 5 V ± 10%.
REV. A
–5–

5 Page

AD5542 arduino
AD5541/AD5542
The AD5542 has an LDAC function that allows the DAC latch
to be updated asynchronously by bringing LDAC low after CS
goes high. LDAC should be maintained high while data is written
to the shift register. Alternatively, LDAC may be tied permanently
low to update the DAC synchronously. With LDAC tied perma-
nently low, the rising edge of CS will load the data to the DAC.
Unipolar Output Operation
These DACs are capable of driving unbuffered loads of 60 k.
Unbuffered operation results in low-supply current, typically
300 µA, and a low-offset error. The AD5541 provides a unipolar
output swing ranging from 0 V to VREF. The AD5542 can be
configured to output both unipolar and bipolar voltages. Figure
19 shows a typical unipolar output voltage circuit. The code
table for this mode of operation is shown in Table I.
+5V
0.1F
+2.5V
10F
0.1F
SERIAL
INTERFACE
VDD REF(REFF*) REFS*
CS
DIN
AD5541/AD5542
OUT
SCLK
LDAC*
DGND
AGND
* AD5542 ONLY
AD820/
OP196
UNIPOLAR
OUTPUT
EXTERNAL
OP AMP
Figure 19. Unipolar Output
Table I. Unipolar Code Table
DAC Latch Contents
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
Analog Output
VREF × (65,535/65,536)
VREF × (32,768/65,536) = 1/2 VREF
VREF × (1/65,536)
0V
Assuming a perfect reference, the worst case output voltage may
be calculated from the following equation.
Unipolar Mode Worst-Case Output
VOUT UNI
=
D
216
× (VREF
+ VGE ) + VZSE
+ INL
where
VOUT–UNI = Unipolar Mode Worst-Case Output
D = Code Loaded to DAC
VREF = Reference Voltage Applied to Part
VGE = Gain Error in Volts
VZSE = Zero Scale Error in Volts
INL = Integral Nonlinearity in Volts
Bipolar Output Operation
With the aid of an external op amp, the AD5542 may be config-
ured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 20. The matched bipolar off-
set resistors RFB and RINV are connected to an external op amp to
achieve this bipolar output swing, typically RFB = RINV = 28 k.
Table II shows the transfer function for this output operating
mode. Also provided on the AD5542 are a set of Kelvin connec-
tions to the analog ground inputs.
+2.5V
+5V
10F
0.1F
0.1F
SERIAL
INTERFACE
VDD
CS
DIN
SCLK
LDAC
RFB
REFF REFS
RFB
INV
RINV
OUT
AD5541/AD5542
DGND AGNDF AGNDS
+5V
BIPOLAR
OUTPUT
–5V
EXTERNAL
OP AMP
Figure 20. Bipolar Output (AD5542 Only)
Table II. Bipolar Code Table
DAC Latch Contents
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
Analog Output
+VREF × (32,767/32,768)
+VREF × (1/32,768)
0V
–VREF × (1/32,768)
–VREF × (32,768/32,768) = –VREF
Assuming a perfect reference, the worst-case bipolar output
voltage may be calculated from the following equation.
Bipolar Mode Worst-Case Output
[( )( ) ( )]VOUTUNI + VOS 2 + RD VREF 1 + RD
VOUTBIP =
( )1 + 2 + RD /A
where
VOS = External Op Amp Input Offset Voltage
RD = RFB and RIN Resistor Matching Error
A = Op Amp Open-Loop Gain
Output Amplifier Selection
For bipolar mode, a precision amplifier should be used, supplied
from a dual power supply. This will provide the ± VREF output.
In a single-supply application, selection of a suitable op amp
may be more difficult as the output swing of the amplifier does
not usually include the negative rail, in this case AGND. This
can result in some degradation of the specified performance
unless the application does not use codes near zero.
The selected op amp needs to have very low-offset voltage, (the
DAC LSB is 38 µV with a 2.5 V reference), to eliminate the
need for output offset trims. Input bias current should also be
very low as the bias current multiplied by the DAC output
impedance (approximately 6K) will add to the zero code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but in order to minimize gain
errors, the input impedance of the output amplifier should be
as high as possible. The amplifier should also have a 3 dB band-
width of 1 MHz or greater. The amplifier adds another time
constant to the system, hence increasing the settling time of the
output. A higher 3 dB amplifier bandwidth results in a shorter
effective settling time of the combined DAC and amplifier.
Force Sense Amplifier Selection
These amplifiers will be single-supply, low-noise amplifiers. A
low-output impedance at high frequencies is preferred as they
need to be able to handle dynamic currents of up to ± 20 mA.
–10–
REV. A

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