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Dual 12-Bit/ High Bandwidth/ Multiplying DAC with 4-Quadrant Resistors and Parallel Interface - AD5405 - Analog Devices

Número de pieza AD5405
Descripción Dual 12-Bit/ High Bandwidth/ Multiplying DAC with 4-Quadrant Resistors and Parallel Interface
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5405 datasheet
AD5405 pdf, arduino
AD5405
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2
Write Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
Data Readback Mode
t10
t11
t12
t13
Limit at TMIN, TMAX
0
0
10
10
0
6
0
5
7
0
0
5
35
5
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns max
ns typ
ns max
Conditions/Comments
R/W to CS setup time
R/W to CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
Address setup time
Address hold time
Data access time
Bus relinquish time
1 See Figure 2. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
2 All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured
with load circuit in Figure 3.
R/W
CS
DACA/DACB
DATA
t1 t2 t8
t3
t4
t9
t5 t10
t2
t11
t6
DATA VALID
t7
Figure 2. Timing Diagram
t12 t13
DATA VALID
200µA
IOL
TO
OUTPUT
PIN
CL
50pF
200µA
IOH
VOH (MIN) + VOL (MAX)
2
Figure 3. Load Circuit for Data Timing Specifications
Rev. 0 | Page 5 of 24





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