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256-Position SPI/I2C Selectable Digital Potentiometer - AD5161 - Analog Devices

Número de pieza AD5161
Descripción 256-Position SPI/I2C Selectable Digital Potentiometer
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5161 datasheet
AD5161 pdf, arduino
Data Sheet
AD5161
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
Symbol Conditions
SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)
Clock Frequency
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulsewidth
fCLK
tCH, tCL
tDS
tDH
tCSS
tCSW
Clock level high or low
CLK Fall to CS Fall Hold Time
tCSH0
CLK Fall to CS Rise Hold Time
tCSH1
CS Rise to Clock Rise Setup
tCS1
I2C INTERFACE TIMING CHARACTERISTICS6, 11 (Specifications Apply to All Parts)
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
fSCL
t1
t2
After this period, the first clock pulse is
generated.
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated START Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
t3
t4
t5
t6
t7
t8
t9
t10
Min Typ1 Max
25
20
5
5
15
40
0
0
10
400
1.3
0.6
1.3
0.6 50
0.6
0.9
100
300
300
0.6
NOTES
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11 See timing diagrams for locations of measured values.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
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