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PDF CY62256 Data sheet ( Hoja de datos )
| Número de pieza | CY62256 | |
| Descripción | 256K (32K x 8) Static RAM | |
| Fabricantes | ART CHIP | |
| Logotipo |  |
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CY62256
256K (32K x 8) Static RAM
Features
Functional Description [1]
z Temperature Ranges
The CY62256 is a high-performance CMOS static RAM
-Commercial:0 to 70
organized as 32K words by 8 bits. Easy memory expansion is
-Industrial: -40 to 85
provided by an active LOW output enable ( ) and active LOW
-Automotive: -40 to 125
output enable ( ) and three-state drives. This device has an
z High speed: 55ns and 70 ns
automatic power-down feature, reducing the power consumption
z Voltage range : 4.5V –5.5V operation
z Low active power (70ns, LL version, Com’l and Ind’l)
-275mW (max)
z Low standby power (70ns,LL Version, Com’l and Ind’l)
-28 µW (max.)
by 99.9% when deselected.
An active Low write enable signal ( ) controls the
writing/reading operation of the memory. When
and
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
z Easy memory expansion with and features
z TTL – compatible inputs and outputs
z Automatic power-down when deselected
z CMOS for optimum speed/power
z Package available in a standard 450-mil-wide (300-mil body
width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead
Reading the device is accomplished by selecting the device and
enabling the outputs,
and active LOW while
remains inactive or HIGH. Under these conditions, the contents
of the location addressed by the information on address pins are
present on the eight data input/output pins. The input/output pins
remain in a high-impedance state unless the chip is selected,
outputs are enabled, and write enable ( ) is HIGH.
reverse TSOP-1, and 600-mial 28-lead PDIP packages.
Logic Block Diagram
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1 page  
Switching Characteristics Over the Operating Range [7]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZOE
tHZCE
tPU
tPD
Write Cycle [10,11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
LOW to Data valid
LOW to Data valid
LOW to Low-Z[8]
HIGH to High-Z[8,9]
LOW to LOW-Z[8]
LOW to LOW-Z[8,9]
LOW to Power-up
HIGH to Power-down
Write Cycle Time
LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
Pulse Width
Data Set-up to write End
Data Hold from Write End
LOW to High-Z[8,9]
HIGH to Low-Z[8]
Switching Waveforms
Read Cycle NO. 1 [12.13]
CY62256
Cy62256-55
Min.
Max.
55
55
5
55
25
5
20
5
20
0
55
55
45
45
0
0
40
25
0
20
5
CY62256-70
Min.
Max.
70
70
5
70
35
5
25
5
25
0
70
70
60
60
0
0
50
30
0
25
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
7.Test conditions assume signal transition time of 5 ns or less, timing reference level is of 1.5V, input pulse levels of 0 to 3V, and output
loading of the specified IOL/IOH and 100-pF load capacitance.
8.At any given temperature and voltage condition, tHZCE is less than tLZOE, and tHZOE is less than tHZCE , and tLZWE for any given device.
9.tHZOE, tHZCE, and tHZWE are specified with CL=5pF as in (b) of AC Test Loads. Transition is measured ±500mV from steady-state
voltage.
10.The internal Write time of the memory is defined by the overlap of LOW and LOW. Both signals must be Low to initiate a
Write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the Write.
11.The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
12.Device is continuously selected. , =VIL.
13. is HIGH for Read cycle.
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5 Page 
Package Diagrams (continued)
28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28
NOTE:ORIENTATION ID MAY BE LOCATED EITHER
AS SHOWN IN OPTION I OR OPTION 2
CY62256
ALL product and company names mentioned in this document are the trademarks of their respective hoders.
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11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY62256.PDF ] | |
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