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PDF i.MX23 Data sheet ( Hoja de datos )
| Número de pieza | i.MX23 | |
| Descripción | Applications Processor | |
| Fabricantes | Freescale Semiconductor | |
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i.MX23 Applications Processor
Reference Manual
IMX23RM
Rev. 1
11/2009
Preliminary—Subject to Change Without Notice
1 page  
Paragraph
Number
Contents
Title
Page
Number
4.4 Clock Frequency Management ........................................................................................ 4-9
4.5 Analog Clock Control ...................................................................................................... 4-9
4.6 CPU and EMI Clock Programming ................................................................................. 4-9
4.7 Chip Reset...................................................................................................................... 4-10
4.8 Programmable Registers ................................................................................................ 4-11
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
Chapter 5
Interrupt Collector
Overview.......................................................................................................................... 5-1
Operation ......................................................................................................................... 5-2
Nesting of Multi-Level IRQ Interrupts........................................................................ 5-4
FIQ Generation ............................................................................................................ 5-6
Interrupt Sources.......................................................................................................... 5-6
CPU Wait-for-Interrupt Mode...................................................................................... 5-9
Behavior During Reset................................................................................................... 5-10
Programmable Registers ................................................................................................ 5-10
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4
Chapter 6
Digital Control and On-Chip RAM
Overview.......................................................................................................................... 6-1
SRAM Controls ............................................................................................................... 6-2
Miscellaneous Controls.................................................................................................... 6-3
Performance Monitoring.............................................................................................. 6-3
High-Entropy PRN Seed.............................................................................................. 6-4
Write-Once Register .................................................................................................... 6-4
Microseconds Counter ................................................................................................. 6-4
Programmable Registers .................................................................................................. 6-4
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
Chapter 7
On-Chip OTP (OCOTP) Controller
Overview.......................................................................................................................... 7-1
Operation ......................................................................................................................... 7-2
Software Read Sequence ............................................................................................. 7-4
Software Write Sequence............................................................................................. 7-5
Write Postamble........................................................................................................... 7-6
Shadow Registers and Hardware Capability Bus ........................................................ 7-6
Behavior During Reset..................................................................................................... 7-7
Programmable Registers .................................................................................................. 7-7
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
iii
5 Page 
Paragraph
Number
Contents
Title
Page
Number
17.1.1
17.1.2
17.2
17.2.1
17.2.2
17.2.3
17.2.3.1
17.2.3.1.1
17.2.3.1.2
17.2.3.1.3
17.2.3.1.4
17.2.4
17.2.5
17.2.6
17.2.7
17.2.8
17.2.9
17.2.10
17.2.11
17.2.12
17.3
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
17.3.6
17.4
Image Support............................................................................................................ 17-2
PXP Limitations/Issues.............................................................................................. 17-3
Operation ....................................................................................................................... 17-3
Pixel Handling ........................................................................................................... 17-4
S0 Cropping/Masking ................................................................................................ 17-5
Scaling ....................................................................................................................... 17-7
Scaling Operation .................................................................................................. 17-8
Bilinear Image Scaling Filter............................................................................. 17-9
YUV 4:2:2 Image Scaling ............................................................................... 17-10
YUV 4:2:0 Image Scaling ............................................................................... 17-11
Out-of-Range Image Access............................................................................ 17-12
Colorspace Conversion............................................................................................ 17-13
Overlays ................................................................................................................... 17-14
Alpha Blending........................................................................................................ 17-16
Color Key................................................................................................................. 17-16
Raster Operations (ROPs)........................................................................................ 17-17
Rotation.................................................................................................................... 17-18
In-place Rendering................................................................................................... 17-20
Interlaced Video Support ......................................................................................... 17-21
Queueing Frame Operations .................................................................................... 17-21
Examples...................................................................................................................... 17-22
Basic QVGA Example............................................................................................. 17-22
Basic QVGA with Overlays .................................................................................... 17-24
Cropped QVGA Example........................................................................................ 17-25
Upscale QVGA to VGA with Overlays................................................................... 17-27
Downscale VGA to WQVGA (480x272) to fill screen........................................... 17-29
Downscale VGA to QVGA with Overlapping Overlays......................................... 17-31
Programmable Registers .............................................................................................. 17-33
18.1
18.2
18.2.1
18.2.1.1
18.2.1.2
18.2.2
18.2.3
18.2.4
18.2.5
Chapter 18
LCD Interface (LCDIF)
Overview........................................................................................................................ 18-1
Operation ....................................................................................................................... 18-1
Bus Interface Mechanisms......................................................................................... 18-3
PIO Operation........................................................................................................ 18-3
Bus Master Operation ............................................................................................ 18-3
Write Datapath ........................................................................................................... 18-4
LCDIF Interrupts ..................................................................................................... 18-10
Initializing the LCDIF ............................................................................................. 18-11
System Interface ...................................................................................................... 18-12
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
ix
11 Page | ||
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