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PDF MC74HC393 Data sheet ( Hoja de datos )

Número de pieza MC74HC393
Descripción Dual 4-Stage Binary Ripple Counter
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MC74HC393
Dual 4−Stage
Binary Ripple Counter
HighPerformance SiliconGate CMOS
The MC54/74HC393 is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4bit binary ripple counters
with parallel outputs from each counter stage. A ÷ 256 counter can be
obtained by cascading the two binary counters.
Internal flipflops are triggered by hightolow transitions of the
clock input. Reset for the counters is asynchronous and activehigh.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used as clocks or as strobes except
when gated with the Clock of the HC393.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 μA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 236 FETs or 59 Equivalent Gates
LOGIC DIAGRAM
CLOCK 1, 13
BINARY
COUNTER
RESET 2, 12
PIN 14 = VCC
PIN 7 = GND
3, 11 Q1
4, 10 Q2
5, 9 Q3
6, 8 Q4
http://onsemi.com
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 63208
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 64606
D SUFFIX
SOIC PACKAGE
CASE 751A03
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
CLOCK a
RESET a
Q1a
Q2a
Q3a
Q4a
GND
1
2
3
4
5
6
7
14 VCC
13 CLOCK b
12 RESET b
11 Q1b
10 Q2b
9 Q3b
8 Q4b
FUNCTION TABLE
Inputs
Clock
Reset
Outputs
XH
L
H L No Change
L L No Change
L No Change
L Advance to
Next State
© Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 7
1
Publication Order Number:
MC74HC393/D

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MC74HC393 pdf
MC74HC393
TIMING DIAGRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
CLOCK
RESET
Q1
Q2
Q3
Q4
Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
COUNT SEQUENCE
Outputs
Q4 Q3 Q2
LLL
LLL
L LH
L LH
LHL
LHL
L HH
L HH
HLL
HLL
HLH
HLH
HH L
HH L
HHH
HHH
Q1
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
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