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PDF AD565A Datasheet ( Hoja de datos )

Número de pieza AD565A
Descripción High Speed 12-Bit Monolithic D/A Converters
Fabricantes Analog Devices 
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AD565A datasheet

1 Page

AD565A pdf
AD566A–SPECIFICATIONS(TA = 25؇C, VEE = –15 V, unless otherwise noted)
Parameter
AD566AJ
Min Typ
Max
AD566AK
Min Typ Max
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
2.0 5.5
0 0.8
120 300
35 100
2.0
0
5.5
0.8
120 300
35 100
RESOLUTION
12 12
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar (Adjustable to Zero per Figure 3)
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
ACCURACY (Error Relative to
Full Scale) 25°C
TMIN to TMAX
–1.6
؎0.8
6
–1.5
–2.0
± 1.0
8
0.01
0.05
25
± 1/4
(0.006)
± 1/2
(0.012)
–2.4
؎1.2
10
0.05
0.15
+10
؎1/2
(0.012)
؎3/4
(0.018)
–1.6
؎0.8
6
–1.5
–2.0
± 1.0
8
0.01
0.05
25
± 1/8
(0.003)
± 1/4
(0.006)
–2.4
؎1.2
10
0.05
0.1
+10
؎0.35
(0.0084)
؎1/2
(0.012)
DIFFERENTIAL NONLINEARITY
25°C
TMIN to TMAX
TEMPERATURE COEFFICIENTS
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
± 1/2 ؎3/4
± 1/4 ؎1/2
MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
12
5 10
7 10
2
12
5 10
35
2
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
250 350
250 350
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
15 30
30 50
15 30
30 50
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY2
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)
–12 –18
15 25
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
–12 –18
15 25
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
± 0.25
± 0.15
± 0.1
± 0.05
؎0.25
؎0.15
± 0.25
± 0.15
± 0.1
± 0.05
؎0.25
؎0.1
REFERENCE INPUT
Input Impedance
15 20 25
15
20 25
POWER DISSIPATION
180 300
180 300
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Reference Voltage
Accuracy
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough)
Output Slew Rate 10%–90%
90%–10%
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage)
Two (2): Bipolar Operation at Digital Input Only
1 V to 10 V, Unipolar
10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
40
5
1
1.5 μs to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth
Small-Signal Closed-Loop Bandwidth
300
1.8
NOTES
1The digital input levels are guaranteed but not tested over the temperature range.
2The power supply gain sensitivity is tested in reference to a VEE of –1.5 V dc.
Specifications subject to change without notice.
Unit
V
V
μA
μA
Bits
mA
mA
kΩ
% of F.S. Range
% of F.S. Range
pF
V
LSB
% of F.S. Range
LSB
% of F.S. Range
LSB
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ns
ns
ns
mA
ppm of F.S./%
V
V
V
V
V
% of F.S. Range
% of F.S. Range
% of F.S. Range
% of F.S. Range
kΩ
mW
kHz typ
mA/μs
mA/μs
kHz
MHz
–4– REV. F

5 Page

AD565A arduino
AD565A
FIGURE 6. OTHER VOLTAGE RANGES
The AD566A can also be easily configured for a unipolar 0 V to
+5 V range or ± 2.5 V and ± 10 V bipolar ranges by using the
additional 5 kΩ application resistor provided at the 20 V span R
terminal, Pin 11. For a 5 V span (0 V to +5 V or ± 2.5 V), the two
5 kΩ resistors are used in parallel by shorting Pin 11 to Pin 9 and
connecting Pin 10 to the op amp output and the bipolar offset
resistor either to ground for unipolar or to VREF for the bipolar
range. For the ±10 V range (20 V span), use the 5 kΩ resistors in
series by connecting only Pin 11 to the op amp output and the
bipolar offset connected as shown. The ± 10 V option is shown
in Figure 6.
R1
5k
BIPOLAR OFF
14k
AD566A
9.95k5k
R2
5k
REF
IN 19.95k
0.5mA
–V 7.5V EREF
AD561
20k
IREF
REF
GND
POWER
GND
5k
IO 8k
DAC
IOUT =
4 ؋ IREF
؋ CODE
CODE
INPUT
20V SPAN
10V SPAN
10pF
DAC
OUT
AD509
2.4k
R3
26k*
–VEE
MSB
LSB
* THE PARALLEL COMBINATION OF THE BIPOLAR OFFSET RESISTOR
AND R3 ESTABLISHES A CURRENT TO BALANCE THE MSB CURRENT.
THE EFFECT OF TEMPERATURE COEFFICIENT MISMATCH BETWEEN
THE BIPOLAR RESISTOR COMBINATION AND DAC RESISTORS IS
EXPANDED ON PREVIOUS PAGE.
Figure 6. ±10 V Voltage Output
Table I. Digital Input Codes
DIGITAL INPUT
MSB
LSB
Straight Binary
ANALOG OUTPUT
Offset Binary
000000000000
011111111111
100000000000
111111111111
Zero
Mid Scale – 1 LSB
+1/2 FS
+FS – l LSB
–FS
Zero – 1 LSB
Zero
+FS – 1 LSB
*Inverts the MSB of the offset binary code with an external inverter to obtain twos complement.
Twos Complement*
Zero
+FS – 1 LSB
–FS
Zero – 1 LSB
–10–
REV.F

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