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PDF AD5545 Datasheet ( Hoja de datos )

Número de pieza AD5545
Descripción 16-/14-Bit DACs
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5545 datasheet

1 Page

AD5545 pdf
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD to GND
VREF to GND
Logic Inputs to GND
V(IOUT) to GND
Input Current to Any Pin except
Supplies
Package Power Dissipation
Thermal Resistance θJA
16-Lead TSSOP
Maximum Junction Temperature
(TJ max)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
RU-16 (Vapor Phase, 60 sec)
RU-16 (Infrared, 15 sec)
Rating
–0.3 V to +8 V
–18 V to +18 V
–0.3 V to +8 V
–0.3 V to VDD + 0.3 V
±50 mA
(TJ max – TA)/θJA
150°C/W
150°C
–40°C to +85°C
–65°C to +150°C
215°C
220°C
AD5545/AD5555
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. I | Page 5 of 23

5 Page

AD5545 arduino
Data Sheet
AD5545/AD5555
Table 7. AD5545 Control Logic Truth Table1, 2
CS CLK LDAC RS MSB Serial Shift Register Function
HX
H
HX
No effect
LL
H
HX
No effect
L + H
HX
Shift register data advanced one bit
LH
H
HX
No effect
+ L
H
HX
No effect
HX
HX
HX
HX
HX
L
H
+
H
H
HX
HX
HX
L0
LH
No effect
No effect
No effect
No effect
No effect
Input Register Function
Latched
Latched
Latched
Latched
Selected DAC updated
with current SR current
Latched
Latched
Latched
Latched data = 0x0000
Latched data = 0x8000
1 SR = shift register, + = positive logic transition, and X = don’t care.
2 At power-on, both the input register and the DAC register are loaded with all 0s.
Table 8. AD5555 Control Logic Truth Table1, 2
CS CLK LDAC RS MSB Serial Shift Register Function
HX
H
HX
No effect
LL
H
HX
No effect
L + H
LH
H
HX
HX
Shift register data advanced one bit
No effect
+ L
H
HX
No effect
HX
HX
HX
HX
HX
L
H
+
H
H
HX
HX
HX
L0
LH
No effect
No effect
No effect
No effect
No effect
Input Register Function
Latched
Latched
Latched
Latched
Selected DAC updated
with current SR current
Latched
Latched
Latched
Latched data = 0x0000
Latched data = 0x2000
1 SR = shift register, + = positive logic transition, and X = don’t care.
2 At power-on, both the input register and the DAC register are loaded with all 0s.
DAC Register
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched data = 0x0000
Latched data = 0x8000
DAC Register
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched data = 0x0000
Latched data = 0x2000
POWER-UP SEQUENCE
It is recommended to power-up VDD and ground prior to any
reference voltages. The ideal power-up sequence is AGNDx, DGND,
VDD, VREFx, and digital inputs. A noncompliance power-up
sequence can elevate reference current, but the device will
resume normal operation once VDD is powered.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 µF to 0.1 µF disc or
chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at VDD to minimize
any transient disturbance and to filter any low frequency ripple
(see Figure 20). Users should not apply switching regulators for
VDD due to the power supply rejection ratio degradation over
frequency.
AD5545/
AD5555
VDD
C2
+ C1
10µF
0.1µF
VDD
AGNDX
DGND
02918-0-008
Figure 20. Power Supply Bypassing and Grounding Connection
GROUNDING
The DGND and AGNDx pins of the AD5545/AD5555 refer to the
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 20).
Rev. I | Page 11 of 23

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